Cristinel Ababei

2009
17	EE	Cristinel Ababei: Parallel placement for FPGAs revisited. FPGA 2009: 280
2006
16	EE	Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Elaheh Bozorgzadeh: Statistical Analysis and Design of HARP FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2088-2102 (2006)
15	EE	Cristinel Ababei, Hushrav Mogal, Kia Bazargan: Three-dimensional place and route for FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1132-1140 (2006)
14	EE	Cristinel Ababei, Kia Bazargan: Non-contiguous linear placement for reconfigurable fabrics. IJES 2(1/2): 86-94 (2006)
2005
13	EE	Cristinel Ababei, Hushrav Mogal, Kia Bazargan: Three-dimensional place and route for FPGAs. ASP-DAC 2005: 773-778
12	EE	Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh: HARP: hard-wired routing pattern FPGAs. FPGA 2005: 21-29
11	EE	Cristinel Ababei, Hushrav Mogal, Kia Bazargan: 3D FPGAs: placement, routing, and architecture evaluation (abstract only). FPGA 2005: 263
10	EE	Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar: Placement and Routing in 3D Integrated Circuits. IEEE Design & Test of Computers 22(6): 520-531 (2005)
9	EE	Pongstorn Maidee, Cristinel Ababei, Kia Bazargan: Timing-driven partitioning-based placement for island style FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 395-406 (2005)
2004
8	EE	Cristinel Ababei: TPR: Three-D Place and Route for FPGAs. FPL 2004: 1172
7	EE	Cristinel Ababei, Pongstorn Maidee, Kia Bazargan: Exploring Potential Benefits of 3D FPGA Integration. FPL 2004: 874-880
6	EE	Cristinel Ababei, Kia Bazargan: Non-Contiguous Linear Placement for Reconfigurable Fabrics. IPDPS 2004
2003
5	EE	Pongstorn Maidee, Cristinel Ababei, Kia Bazargan: Fast timing-driven partitioning-based placement for island style FPGAs. DAC 2003: 598-603
4	EE	Cristinel Ababei, Kia Bazargan: Placement Method Targeting Predictability Robustness and Performance. ICCAD 2003: 81-85
3	EE	Cristinel Ababei, Kia Bazargan: Timing Minimization by Statistical Timing hMetis-based Partitioning. VLSI Design 2003: 58-63
2002
2	EE	Cristinel Ababei, Kia Bazargan: Statistical Timing Driven Partitioning for VLSI Circuits. DATE 2002: 1109
1	EE	Cristinel Ababei, Navaratnasothie Selvakkumaran, Kia Bazargan, George Karypis: Multi-objective circuit partitioning for cutsize and path-based delay minimization. ICCAD 2002: 181-185

Coauthor Index

1	Kia Bazargan	[1] [2] [3] [4] [5] [6] [7] [9] [10] [11] [12] [13] [14] [15] [16]
2	Elaheh Bozorgzadeh (Eli Bozorgzadeh)	[12] [16]
3	Yan Feng	[10]
4	Brent Goplen	[10]
5	George Karypis	[1]
6	Ryan Kastner	[12] [16]
7	Pongstorn Maidee	[5] [7] [9]
8	Hushrav Mogal	[10] [11] [13] [15]
9	Sachin S. Sapatnekar	[10]
10	Navaratnasothie Selvakkumaran	[1]
11	Satish Sivaswamy	[12] [16]
12	Gang Wang	[12] [16]
13	Tianpei Zhang	[10]