Bipul Chandra Paul

Bipul C. Paul

2008
26	EE	Bipul Chandra Paul, Shinobu Fujita, Masaki Okajima: ROM based logic (RBL) design: High-performance and low-power adders. ISCAS 2008: 796-799
2007
25	EE	Mridul Agarwal, Bipul C. Paul, Ming Zhang, Subhasish Mitra: Circuit Failure Prediction and Its Application to Transistor Aging. VTS 2007: 277-286
24	EE	Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy: Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 743-751 (2007)
23	EE	Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee: Prospect of ballistic CNFET in high performance applications: Modeling and analysis. JETC 3(3): (2007)
2006
22	EE	Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee: Modeling and analysis of circuit performance of ballistic CNFET. DAC 2006: 717-722
21	EE	Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy: Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits. DATE 2006: 780-785
20	EE	Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy: Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies. DATE 2006: 856-861
19	EE	Kunhyuk Kang, Bipul C. Paul, Kaushik Roy: Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters. ACM Trans. Design Autom. Electr. Syst. 11(4): 848-879 (2006)
18	EE	Aditya Bansal, Bipul Chandra Paul, Kaushik Roy: An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2765-2774 (2006)
17	EE	Bipul Chandra Paul, Amit Agarwal, Kaushik Roy: Low-power design techniques for scaled technologies. Integration 39(2): 64-89 (2006)
16	EE	Bipul C. Paul, Kaushik Roy: Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits. J. Electronic Testing 22(2): 115-124 (2006)
2005
15	EE	Kunhyuk Kang, Bipul Chandra Paul, Kaushik Roy: Statistical Timing Analysis using Levelized Covariance Propagation. DATE 2005: 764-769
14	EE	Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy: A process-tolerant cache architecture for improved yield in nanoscale technologies. IEEE Trans. VLSI Syst. 13(1): 27-38 (2005)
13	EE	Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy: Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation. IEEE Trans. VLSI Syst. 13(11): 1213-1224 (2005)
2004
12	EE	Woopyo Jeong, Bipul Chandra Paul, Kaushik Roy: Adaptive supply voltage technique for low swing interconnects. ASP-DAC 2004: 284-287
11	EE	Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy: Novel sizing algorithm for yield improvement under process variation in nanometer technology. DAC 2004: 454-459
10	EE	Amit Agarwal, Bipul Chandra Paul, Kaushik Roy: A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies. IOLTS 2004: 149-154
9	EE	Bipul Chandra Paul, Arijit Raychowdhury, Kaushik Roy: Device optimization for ultra-low power digital sub-threshold operation. ISLPED 2004: 96-101
8	EE	Bipul Chandra Paul, Cassondra Neau, Kaushik Roy: Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits. ITC 2004: 1269-1275
7	EE	Naran Sirisantana, Bipul Chandra Paul, Kaushik Roy: Enhancing Yield at the End of the Technology Roadmap. IEEE Design & Test of Computers 21(6): 563-571 (2004)
2002
6	EE	Bipul Chandra Paul, Kaushik Roy: Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis. ITC 2002: 384-390
5	EE	Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy: Dynamic Noise Analysis with Capacitive and Inductive Coupling. VLSI Design 2002: 65-70
2001
4	EE	Bipul Chandra Paul, Seung Hoon Choi, Yonghee Im, Kaushik Roy: Design Verification and Robust Design Technique for Cross-Talk Faults. Asian Test Symposium 2001: 449-
3	EE	Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul: Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic. VLSI Design 2001: 211-214
2	EE	Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul: Robust subthreshold logic for ultra-low power operation. IEEE Trans. VLSI Syst. 9(1): 90-99 (2001)
2000
1	EE	Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul: Robust ultra-low power sub-threshold DTMOS logic. ISLPED 2000: 25-30

Coauthor Index

1	Amit Agarwal	[10] [14] [17]
2	Mridul Agarwal	[25]
3	Muhammad Ashraful Alam	[21] [24]
4	Aditya Bansal	[18]
5	Swarup Bhunia	[13] [20]
6	Seung Hoon Choi	[4] [5] [11]
7	Animesh Datta	[14]
8	Shinobu Fujita	[22] [23] [26]
9	Yonghee Im	[4]
10	Woopyo Jeong	[12]
11	Kunhyuk Kang	[15] [19] [21] [24]
12	Haldun Kufluoglu	[21] [24]
13	Thomas Lee	[22] [23]
14	Hamid Mahmoodi (Hamid Mahmoodi-Meimand)	[14]
15	Subhasish Mitra	[25]
16	Cassondra Neau	[8]
17	Masaki Okajima	[22] [23] [26]
18	Arijit Raychowdhury	[9] [13] [20]
19	Kaushik Roy	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [24]
20	Naran Sirisantana	[7]
21	Hendrawan Soeleman	[1] [2] [3]
22	Ming Zhang	[25]