| 2009 |
|---|
| 102 | EE | Debasish Das,
William Scott,
Shahin Nazarian,
Hai Zhou:
An efficient current-based logic cell model for crosstalk delay analysis.
ISQED 2009: 627-633 |
| 2008 |
|---|
| 101 | EE | Nikolaos D. Liveris,
Hai Zhou,
Prithviraj Banerjee:
A dynamic-programming algorithm for reducing the energy consumption of pipelined System-Level streaming applications.
ASP-DAC 2008: 42-48 |
| 100 | EE | Debasish Das,
Kip Killpack,
Chandramouli V. Kashyap,
Abhijit Jas,
Hai Zhou:
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering.
ASP-DAC 2008: 486-491 |
| 99 | EE | Jia Wang,
Hai Zhou:
An efficient incremental algorithm for min-area retiming.
DAC 2008: 528-533 |
| 98 | EE | Nikolaos D. Liveris,
Hai Zhou,
Robert P. Dick,
Prithviraj Banerjee:
State space abstraction for parameterized self-stabilizing embedded systems.
EMSOFT 2008: 11-20 |
| 97 | EE | Jia Wang,
Hai Zhou:
Linear constraint graph for floorplan optimization with soft blocks.
ICCAD 2008: 9-15 |
| 96 | EE | Jieyi Long,
Hai Zhou,
Seda Ogrenci Memik:
An O(nlogn) edge-based algorithm for obstacle-avoiding rectilinear steiner tree construction.
ISPD 2008: 126-133 |
| 95 | EE | Hai Zhou:
Circuit Retiming.
Encyclopedia of Algorithms 2008 |
| 94 | EE | Hai Zhou:
Circuit Retiming: An Incremental Approach.
Encyclopedia of Algorithms 2008 |
| 93 | EE | Hai Zhou:
Rectilinear Spanning Tree.
Encyclopedia of Algorithms 2008 |
| 92 | EE | Hai Zhou:
Rectilinear Steiner Tree.
Encyclopedia of Algorithms 2008 |
| 91 | EE | Hai Zhou:
A new efficient retiming algorithm derived by formal manipulation.
ACM Trans. Design Autom. Electr. Syst. 13(1): (2008) |
| 90 | EE | Chiu-Wing Sham,
Evangeline F. Y. Young,
Hai Zhou:
Optimizing wirelength and routability by searching alternative packings in floorplanning.
ACM Trans. Design Autom. Electr. Syst. 13(1): (2008) |
| 89 | EE | Ruiming Chen,
Hai Zhou:
Fast Estimation of Timing Yield Bounds for Process Variations.
IEEE Trans. VLSI Syst. 16(3): 241-248 (2008) |
| 88 | EE | Jieyi Long,
Hai Zhou,
Seda Ogrenci Memik:
EBOARST: An Efficient Edge-Based Obstacle-Avoiding Rectilinear Steiner Tree Construction Algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2169-2182 (2008) |
| 2007 |
|---|
| 87 | | Hai Zhou,
Enrico Macii,
Zhiyuan Yan,
Yehia Massoud:
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007
ACM 2007 |
| 86 | EE | Debasish Das,
Ahmed Shebaita,
Yehea I. Ismail,
Hai Zhou,
Kip Killpack:
NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits.
ACM Great Lakes Symposium on VLSI 2007: 25-30 |
| 85 | EE | Jia Wang,
Ming-Yang Kao,
Hai Zhou:
Address generation for nanowire decoders.
ACM Great Lakes Symposium on VLSI 2007: 525-528 |
| 84 | EE | Ruiming Chen,
Hai Zhou:
Fast Buffer Insertion for Yield Optimization Under Process Variations.
ASP-DAC 2007: 19-24 |
| 83 | EE | Ruiming Chen,
Hai Zhou:
New Block-Based Statistical Timing Analysis Approaches Without Moment Matching.
ASP-DAC 2007: 462-467 |
| 82 | EE | Nikolaos D. Liveris,
Chuan Lin,
J. Wang,
Hai Zhou,
Prithviraj Banerjee:
Retiming for Synchronous Data Flow Graphs.
ASP-DAC 2007: 480-485 |
| 81 | EE | Chuan Lin,
Hai Zhou:
Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains.
ASP-DAC 2007: 541-546 |
| 80 | EE | Ruiming Chen,
Hai Zhou:
Fast Min-Cost Buffer Insertion under Process Variations.
DAC 2007: 338-343 |
| 79 | EE | Chuan Lin,
Aiguo Xie,
Hai Zhou:
Design closure driven delay relaxation based on convex cost network flow.
DATE 2007: 63-68 |
| 78 | EE | Jia Wang,
Debasish Das,
Hai Zhou:
Gate sizing by Lagrangian relaxation revisited.
ICCAD 2007: 111-118 |
| 77 | EE | Ruiming Chen,
Hai Zhou:
Timing budgeting under arbitrary process variations.
ICCAD 2007: 344-349 |
| 76 | EE | Pingqiang Zhou,
Yuchun Ma,
Zhuoyuan Li,
Robert P. Dick,
Li Shang,
Hai Zhou,
Xianlong Hong,
Qiang Zhou:
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits.
ICCAD 2007: 590-597 |
| 75 | EE | Debjit Sinha,
Jianfeng Luo,
Subramanian Rajagopalan,
Shabbir H. Batterywala,
Narendra V. Shenoy,
Hai Zhou:
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects.
VLSI Design 2007: 875-880 |
| 74 | EE | Ruiming Chen,
Hai Zhou:
An Effective Algorithm for Buffer Insertion in General Circuits Based on Network Flow.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2069-2073 (2007) |
| 73 | EE | Arindam Mallik,
Debjit Sinha,
Prithviraj Banerjee,
Hai Zhou:
Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 447-455 (2007) |
| 72 | EE | Chuan Lin,
Hai Zhou:
Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1222-1232 (2007) |
| 71 | EE | Jia Wang,
Hai Zhou:
Optimal Jumper Insertion for Antenna Avoidance Considering Antenna Charge Sharing.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1445-1453 (2007) |
| 70 | EE | Debjit Sinha,
Hai Zhou,
Narendra V. Shenoy:
Advances in Computation of the Maximum of a Set of Gaussian Random Variables.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1522-1533 (2007) |
| 69 | EE | Zhenyu (Peter) Gu,
Jia Wang,
Robert P. Dick,
Hai Zhou:
Unified Incremental Physical-Level and High-Level Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1576-1588 (2007) |
| 2006 |
|---|
| 68 | | Gang Qu,
Yehea I. Ismail,
Narayanan Vijaykrishnan,
Hai Zhou:
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006
ACM 2006 |
| 67 | EE | Jia Wang,
Hai Zhou:
Optimal jumper insertion for antenna avoidance under ratio upper-bound.
DAC 2006: 761-766 |
| 66 | EE | Chuan Lin,
Hai Zhou:
An efficient retiming algorithm under setup and hold constraints.
DAC 2006: 945-950 |
| 65 | EE | Arindam Mallik,
Debjit Sinha,
Prithviraj Banerjee,
Hai Zhou:
Smart bit-width allocation for low power optimization in a systemc based ASIC design environment.
DATE 2006: 618-623 |
| 64 | EE | Chuan Lin,
Hai Zhou,
Chris C. N. Chu:
A revisit to floorplan optimization by Lagrangian relaxation.
ICCAD 2006: 164-171 |
| 63 | EE | Debjit Sinha,
DiaaEldin Khalil,
Yehea I. Ismail,
Hai Zhou:
A timing dependent power estimation framework considering coupling.
ICCAD 2006: 401-407 |
| 62 | EE | Debasish Das,
Ahmed Shebaita,
Hai Zhou,
Yehea I. Ismail,
Kip Killpack:
FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling.
ICCD 2006 |
| 61 | EE | Debjit Sinha,
Hai Zhou,
Narendra V. Shenoy:
Advances in Computation of the Maximum of a Set of Random Variables.
ISQED 2006: 306-311 |
| 60 | EE | Jia Wang,
Hai Zhou,
Ping-Chih Wu:
Processing Rate Optimization by Sequential System Floorplanning.
ISQED 2006: 340-345 |
| 59 | EE | Serkan Ozdemir,
Debjit Sinha,
Gokhan Memik,
Jonathan Adams,
Hai Zhou:
Yield-Aware Cache Architectures.
MICRO 2006: 15-25 |
| 58 | EE | Debjit Sinha,
Narendra V. Shenoy,
Hai Zhou:
Statistical Timing Yield Optimization by Gate Sizing.
IEEE Trans. VLSI Syst. 14(10): 1140-1146 (2006) |
| 57 | EE | Chuan Lin,
Jia Wang,
Hai Zhou:
Clustering for Processing Rate Optimization.
IEEE Trans. VLSI Syst. 14(11): 1264-1275 (2006) |
| 56 | EE | Debjit Sinha,
Hai Zhou:
Statistical Timing Analysis With Coupling.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2965-2975 (2006) |
| 55 | EE | Ruiming Chen,
Hai Zhou:
An Efficient Data Structure for Maxplus Merge in Dynamic Programming.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 3004-3009 (2006) |
| 54 | EE | Debjit Sinha,
Hai Zhou:
Gate-size optimization under timing constraints for coupling-noise reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1064-1074 (2006) |
| 53 | EE | Chuan Lin,
Hai Zhou:
Optimal wire retiming without binary search.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1577-1588 (2006) |
| 52 | EE | Ruiming Chen,
Hai Zhou:
Statistical timing verification for transparently latched circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1847-1855 (2006) |
| 2005 |
|---|
| 51 | EE | Jia Wang,
Hai Zhou:
Interconnect estimation without packing via ACG floorplans.
ASP-DAC 2005: 1152-1155 |
| 50 | EE | Debjit Sinha,
Hai Zhou:
Yield driven gate sizing for coupling-noise reduction under uncertainty.
ASP-DAC 2005: 192-197 |
| 49 | EE | Hai Zhou:
Deriving a new efficient algorithm for min-period retiming.
ASP-DAC 2005: 990-993 |
| 48 | EE | Nikolaos D. Liveris,
Hai Zhou,
Prithviraj Banerjee:
An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications.
Asian Test Symposium 2005: 28-33 |
| 47 | EE | Xiaoyong Tang,
Hai Zhou,
Prithviraj Banerjee:
Leakage power optimization with dual-Vth library in high-level synthesis.
DAC 2005: 202-207 |
| 46 | EE | Zhenyu (Peter) Gu,
Jia Wang,
Robert P. Dick,
Hai Zhou:
Incremental exploration of the combined physical and behavioral design space.
DAC 2005: 208-213 |
| 45 | | Debjit Sinha,
Narendra V. Shenoy,
Hai Zhou:
Statistical gate sizing for timing yield optimization.
ICCAD 2005: 1037-1041 |
| 44 | | Chuan Lin,
Jia Wang,
Hai Zhou:
Clustering for processing rate optimization.
ICCAD 2005: 189-195 |
| 43 | | Ruiming Chen,
Hai Zhou:
Efficient algorithms for buffer insertion in general circuits based on network flow.
ICCAD 2005: 322-326 |
| 42 | | Chuan Lin,
Hai Zhou:
Trade-off between latch and flop for min-period sequential circuit designs with crosstalk.
ICCAD 2005: 329-334 |
| 41 | | Debjit Sinha,
Hai Zhou:
A unified framework for statistical timing analysis with coupling and multiple input switching.
ICCAD 2005: 837-843 |
| 40 | EE | Min Pan,
Chris C. N. Chu,
Hai Zhou:
Timing yield estimation using statistical static timing analysis.
ISCAS (3) 2005: 2461-2464 |
| 39 | EE | Chuan Lin,
Hai Zhou:
Wire retiming as fixpoint computation.
IEEE Trans. VLSI Syst. 13(12): 1340-1348 (2005) |
| 38 | EE | Qi Zhu,
Hai Zhou,
Tong Jing,
Xianlong Hong,
Yang Yang:
Spanning graph-based nonrectilinear steiner tree algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1066-1075 (2005) |
| 2004 |
|---|
| 37 | EE | Jia Wang,
Hai Zhou:
Minimal period retiming under process variations.
ACM Great Lakes Symposium on VLSI 2004: 131-135 |
| 36 | EE | Qi Zhu,
Hai Zhou,
Tong Jing,
Xianlong Hong,
Yang Yang:
Efficient octilinear Steiner tree construction based on spanning graphs.
ASP-DAC 2004: 687-690 |
| 35 | EE | Chuan Lin,
Hai Zhou:
Wire Retiming for System-on-Chip by Fixpoint Computation.
DATE 2004: 1092-1097 |
| 34 | EE | Debjit Sinha,
Hai Zhou:
Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation.
ICCAD 2004: 14-19 |
| 33 | EE | Ruiming Chen,
Hai Zhou:
Timing macro-modeling of IP blocks with crosstalk.
ICCAD 2004: 155-159 |
| 32 | EE | Chuan Lin,
Hai Zhou:
Optimal wire retiming without binary search.
ICCAD 2004: 452-458 |
| 31 | EE | Ruiming Chen,
Hai Zhou:
Clock schedule verification under process variations.
ICCAD 2004: 619-625 |
| 30 | EE | Ruiming Chen,
Hai Zhou:
A Flexible Data Structure for Efficient Buffer Insertion.
ICCD 2004: 216-221 |
| 29 | EE | Hai Zhou,
Jia Wang:
ACG-Adjacent Constraint Graph for General Floorplans.
ICCD 2004: 572-575 |
| 28 | EE | Debjit Sinha,
Hai Zhou,
Chris C. N. Chu:
Optimal gate sizing for coupling-noise reduction.
ISPD 2004: 176-181 |
| 27 | EE | Hai Zhou:
Efficient Steiner tree construction based on spanning graphs.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 704-710 (2004) |
| 26 | EE | Hai Zhou,
Chuan Lin:
Retiming for wire pipelining in system-on-chip.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1338-1345 (2004) |
| 2003 |
|---|
| 25 | EE | Hai Zhou:
Timing Verification with Crosstalk for Transparently Latched Circuits.
DATE 2003: 10056-10061 |
| 24 | EE | Chuan Lin,
Hai Zhou:
Retiming for Wire Pipelining in System-On-Chip.
ICCAD 2003: 215-220 |
| 23 | EE | Hai Zhou:
Efficient Steiner tree construction based on spanning graphs.
ISPD 2003: 152-157 |
| 22 | EE | Anuj Goel,
Khurram Sajid,
Hai Zhou,
Adnan Aziz,
Vigyan Singhal:
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions.
Formal Methods in System Design 22(3): 205-224 (2003) |
| 21 | EE | Hai Zhou:
Timing analysis with crosstalk is a fixpoint on a complete lattice.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1261-1269 (2003) |
| 2002 |
|---|
| 20 | EE | Shabbir H. Batterywala,
Narendra V. Shenoy,
William Nicholls,
Hai Zhou:
Track assignment: a desirable intermediate step between global routing and detailed routing.
ICCAD 2002: 59-66 |
| 19 | EE | Hai Zhou:
Clock schedule verification with crosstalk.
Timing Issues in the Specification and Synthesis of Digital Systems 2002: 78-83 |
| 18 | EE | Hai Zhou,
Narendra V. Shenoy,
William Nicholls:
Efficient minimum spanning tree construction without Delaunay triangulation.
Inf. Process. Lett. 81(5): 271-276 (2002) |
| 2001 |
|---|
| 17 | EE | Hai Zhou,
Narendra V. Shenoy,
William Nicholls:
Efficient minimum spanning tree construction without Delaunay triangulation.
ASP-DAC 2001: 192-197 |
| 16 | EE | Hai Zhou,
Narendra V. Shenoy,
William Nicholls:
Timing Analysis with Crosstalk as Fixpoints on Complete Lattice.
DAC 2001: 714-719 |
| 15 | EE | Hai Zhou,
Adnan Aziz:
Buffer minimization in pass transistor logic.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(5): 693-697 (2001) |
| 2000 |
|---|
| 14 | EE | Hai Zhou,
D. F. Wong:
Optimal low power X OR gate decomposition.
DAC 2000: 104-107 |
| 13 | EE | Hai Zhou,
Adnan Aziz:
Buffer minimization in pass transistor logic.
ISPD 2000: 105-110 |
| 12 | EE | Hai Zhou,
Martin D. F. Wong,
I-Min Liu,
Adnan Aziz:
Simultaneous routing and buffer insertion with restrictions onbuffer locations.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(7): 819-824 (2000) |
| 1999 |
|---|
| 11 | EE | Hai Zhou,
D. F. Wong,
I-Min Liu,
Adnan Aziz:
Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations.
DAC 1999: 96-99 |
| 10 | EE | Hung-Ming Chen,
Hai Zhou,
Fung Yu Young,
D. F. Wong,
Hannah Honghua Yang,
Naveed A. Sherwani:
Integrated floorplanning and interconnect planning.
ICCAD 1999: 354-357 |
| 9 | EE | I-Min Liu,
Adnan Aziz,
D. F. Wong,
Hai Zhou:
An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation.
ICCD 1999: 210-215 |
| 8 | EE | Hai Zhou,
Martin D. F. Wong:
Global routing with crosstalk constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1683-1688 (1999) |
| 1998 |
|---|
| 7 | | Anuj Goel,
Khurram Sajid,
Hai Zhou,
Adnan Aziz,
Vigyan Singhal:
BDD Based Procedures for a Theory of Equality with Uninterpreted Functions.
CAV 1998: 244-255 |
| 6 | EE | Hai Zhou,
D. F. Wong:
Global Routing with Crosstalk Constraints.
DAC 1998: 374-377 |
| 5 | EE | Hai Zhou,
D. F. Wong:
Optimal river routing with crosstalk constraints.
ACM Trans. Design Autom. Electr. Syst. 3(3): 496-514 (1998) |
| 1997 |
|---|
| 4 | EE | Hai Zhou,
D. F. Wong:
An exact gate decomposition algorithm for low-power technology mapping.
ICCAD 1997: 575-580 |
| 3 | | Hai Zhou,
D. F. Wong:
Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation.
ICCD 1997: 628-633 |
| 1996 |
|---|
| 2 | EE | Hai Zhou,
D. F. Wong:
An optimal algorithm for river routing with crosstalk constraints.
ICCAD 1996: 310-315 |
| 1 | EE | Chung-Ping Chen,
Hai Zhou,
D. F. Wong:
Optimal non-uniform wire-sizing under the Elmore delay model.
ICCAD 1996: 38-43 |
