Xun Liu

2009
30	EE	Taemin Kim, Xun Liu: Better than optimum?: register reduction using idle pipelined functional units. ACM Great Lakes Symposium on VLSI 2009: 327-332
2008
29	EE	Lixia Yang, Xun Liu, Changyong Xu: Hindrances to the Development of Tourism E-Commerce in China. ISECS 2008: 588-591
28	EE	Xun Liu, Nicholas A. Steinmetz, Alison B. Farley, Charles D. Smith, Jane E. Joseph: Mid-fusiform Activation during Object Discrimination Reflects the Process of Differentiating Structural Descriptions. J. Cognitive Neuroscience 20(9): 1711-1726 (2008)
2007
27	EE	Zhentao Yu, Marios C. Papaefthymiou, Xun Liu: Skew spreading for peak current reduction. ACM Great Lakes Symposium on VLSI 2007: 461-464
26	EE	Zhengtao Yu, Xun Liu: Design of Rotary Clock Based Circuits. DAC 2007: 43-48
25	EE	Taemin Kim, Xun Liu: Compatibility path based binding algorithm for interconnect reduction in high level synthesis. ICCAD 2007: 435-441
24	EE	Xun Liu, Yuantao Peng, Marios C. Papaefthymiou: RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power CoRR abs/0710.4690: (2007)
23	EE	Zhengtao Yu, Xun Liu: Low-Power Rotary Clock Array Design. IEEE Trans. VLSI Syst. 15(1): 5-12 (2007)
2006
22	EE	Yuantao Peng, Xun Liu: Low-power repeater insertion with both delay and slew rate constraints. DAC 2006: 302-307
21	EE	Lifang Wu, Xianglong Meng, Xun Liu, Shiju Chen: A New Method of Object Segmentation in the Basketball Videos. ICPR (1) 2006: 319-322
20	EE	Yuantao Peng, Xun Liu: An Efficient Low-Power Repeater-Insertion Scheme. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2726-2736 (2006)
19	EE	Xun Liu, Yuantao Peng, Marios C. Papaefthymiou: Practical repeater insertion for low power: what repeater library do we need? IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 917-924 (2006)
2005
18	EE	Yuantao Peng, Xun Liu: A sensitivity analysis of low-power repeater insertion. ACM Great Lakes Symposium on VLSI 2005: 244-247
17	EE	Yuantao Peng, Xun Liu: Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method. DAC 2005: 813-818
16	EE	Xun Liu, Yuantao Peng, Marios C. Papaefthymiou: RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power. DATE 2005: 1330-1335
15	EE	Zhengtao Yu, Xun Liu: Power Analysis of Rotary Clock. ISVLSI 2005: 150-155
14	EE	Yuantao Peng, Xun Liu: RITC: Repeater Insertion with Timing Target Compensation. ISVLSI 2005: 299-300
13	EE	Xun Liu, Yang Gao, Dong Shao, Ruili Wang: Feedback based Dynamic Autonomous Web Service Composition. SKG 2005: 19
12	EE	Xun Liu, Marios C. Papaefthymiou: HyPE: hybrid power estimation for IP-based systems-on-chip. IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1089-1103 (2005)
2004
11	EE	Yuantao Peng, Xun Liu: Power macromodeling of global interconnects considering practical repeater insertion. ACM Great Lakes Symposium on VLSI 2004: 244-247
10	EE	Xun Liu, Yuantao Peng, Marios C. Papaefthymiou: Practical repeater insertion for low power: what repeater library do we need? DAC 2004: 30-35
9	EE	Xun Liu, Marios C. Papaefthymiou: A Markov chain sequence generator for power macromodeling. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1048-1062 (2004)
2003
8	EE	Xun Liu, Marios C. Papaefthymiou: Design of a 20-mb/s 256-state Viterbi decoder. IEEE Trans. VLSI Syst. 11(6): 965-975 (2003)
2002
7	EE	Xun Liu, Marios C. Papaefthymiou: Design of a high-throughput low-power IS95 Viterbi decoder. DAC 2002: 263-268
6	EE	Xun Liu, Marios C. Papaefthymiou: A Markov chain sequence generator for power macromodeling. ICCAD 2002: 404-411
5	EE	Xun Liu, Marios C. Papaefthymiou: Incorporation of input glitches into power macromodeling. ISCAS (4) 2002: 846-849
4	EE	Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman: Retiming and clock scheduling for digital circuit optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 184-203 (2002)
2001
3	EE	Xun Liu, Marios C. Papaefthymiou: A static power estimation methodolodgy for IP-based design. DATE 2001: 280-289
1999
2	EE	Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman: Maximizing Performance by Retiming and Clock Skew Scheduling. DAC 1999: 231-236
1	EE	Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman: Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits. DATE 1999: 643-649

Coauthor Index

1	Shiju Chen	[21]
2	Alison B. Farley	[28]
3	Eby G. Friedman	[1] [2] [4]
4	Yang Gao	[13]
5	Jane E. Joseph	[28]
6	Taemin Kim	[25] [30]
7	Xianglong Meng	[21]
8	Marios C. Papaefthymiou	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [12] [16] [19] [24] [27]
9	Yuantao Peng	[10] [11] [14] [16] [17] [18] [19] [20] [22] [24]
10	Dong Shao	[13]
11	Charles D. Smith	[28]
12	Nicholas A. Steinmetz	[28]
13	Ruili Wang	[13]
14	Lifang Wu	[21]
15	Changyong Xu	[29]
16	Lixia Yang	[29]
17	Zhengtao Yu	[15] [23] [26]
18	Zhentao Yu	[27]

Colors in the list of coauthors