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Ching-Te Chuang

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2008
34EEAditya Bansal, Rama N. Singh, Saibal Mukhopadhyay, Geng Han, Fook-Luen Heng, Ching-Te Chuang: Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield. ICCD 2008: 457-462
33EESaibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang: Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. ISCAS 2008: 384-387
32EESaibal Mukhopadhyay, Rajiv V. Joshi, Keunwoo Kim, Ching-Te Chuang: Variability Analysis for sub-100nm PD/SOI Sense-Amplifier. ISQED 2008: 488-491
31EEAmlan Ghosh, Rahul M. Rao, Ching-Te Chuang, Richard B. Brown: On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits. ISQED 2008: 815-820
30EEAditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy: Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. VLSI Design 2008: 125-130
29EEAmlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown: On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit. VLSI Design 2008: 143-149
28EENiladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy: Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. VTS 2008: 101-106
27EEJente B. Kuang, Keunwoo Kim, Ching-Te Chuang, Hung C. Ngo, F. H. Gebara, Kevin J. Nowka: Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies. IEEE Trans. VLSI Syst. 16(12): 1657-1665 (2008)
2007
26EESaibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang: Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies. ISLPED 2007: 20-25
25EERajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Q. Williams, Ching-Te Chuang: A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies. ISLPED 2007: 8-13
24EEJie Deng, Keunwoo Kim, Ching-Te Chuang, H.-S. Philip Wong: Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI. ISQED 2007: 145-152
23EERajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang: A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology. VLSI Design 2007: 665-672
22EESaibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy: Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices. Microelectronics Journal 38(8-9): 931-941 (2007)
2006
21EEKoushik K. Das, Shih-Hsien Lo, Ching-Te Chuang: High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header. VLSI Design 2006: 758-761
20EESaibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy: Modeling and Analysis of Leakage Currents in Double-Gate Technologies. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2052-2061 (2006)
2005
19EESaibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy: Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits. ISLPED 2005: 8-13
18EESaibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy: Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. ISQED 2005: 410-415
17EERajiv V. Joshi, S. S. Kang, N. Zamdmar, A. Mocuta, Ching-Te Chuang, J. A. Pascual-Gutiérrez: Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies. VLSI Design 2005: 697-702
2004
16EEKeunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang: Nanoscale CMOS circuit leakage power reduction by double-gate device. ISLPED 2004: 102-107
15EERajiv V. Joshi, K. Kroell, Ching-Te Chuang: A Novel Technique For Steady State Analysis For VLSI Circuits In Partially Depleted SOI. VLSI Design 2004: 832-
2003
14EEKerry Bernstein, Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri: Design and CAD Challenges in sub-90nm CMOS Technologies. ICCAD 2003: 129-137
13EEKoushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown: New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology. ISLPED 2003: 168-171
12EEKeunwoo Kim, Rajiv V. Joshi, Ching-Te Chuang: Strained-si devices and circuits for low-power applications. ISLPED 2003: 180-183
11EEChing-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim: Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits. ISQED 2003: 153-158
10EERajiv V. Joshi, Ching-Te Chuang, S. K. H. Fung, Fari Assaderaghi, Melanie Sherony, I. Yang, Ghavam V. Shahidi: PD/SOI SRAM performance in presence of gate-to-body tunneling current. IEEE Trans. VLSI Syst. 11(6): 1106-1113 (2003)
9EER. Rodríguez, James H. Stathis, Barry P. Linder, Rajiv V. Joshi, Ching-Te Chuang: Influence and model of gate oxide breakdown on CMOS inverters. Microelectronics Reliability 43(9-11): 1439-1444 (2003)
2002
8EER. Rodríguez, James H. Stathis, Barry P. Linder, S. Kowalczyk, Ching-Te Chuang, Rajiv V. Joshi, Gregory A. Northrop, Kerry Bernstein, A. J. Bhavnagarwala, Salvatore Lombardo: Analysis of the effect of the gate oxide breakdown on SRAM stability. Microelectronics Reliability 42(9-11): 1445-1448 (2002)
2001
7EERajiv V. Joshi, Wei Hwang, Ching-Te Chuang: SOI for asynchronous dynamic circuits. ACM Great Lakes Symposium on VLSI 2001: 37-42
2000
6EERajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang: "Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). ISLPED 2000: 203-206
5EERajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang: A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology. VLSI Design 2000: 44-49
4EERuchir Puri, Ching-Te Chuang: SOI Digital Circuits: Design Issues. VLSI Design 2000: 474-479
1999
3EEChing-Te Chuang, Ruchir Puri: SOI Digital CMOS VLSI - a Design Perspective. DAC 1999: 709-714
2EERuchir Puri, Ching-Te Chuang: Hysteresis effect in floating-body partially-depleted SOI CMOS domino circuits. ISLPED 1999: 223-228
1997
1EELeon J. Sigal, James D. Warnock, Brian W. Curran, Yuen H. Chan, Peter J. Camporese, Mark D. Mayo, William V. Huott, Daniel R. Knebel, Ching-Te Chuang, James P. Eckhardt, Philip T. Wu: Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor. IBM Journal of Research and Development 41(4&5): 489-504 (1997)

Coauthor Index

1Fari Assaderaghi [10]
2Aditya Bansal [30] [34]
3Kerry Bernstein [8] [14]
4A. J. Bhavnagarwala [8]
5Richard B. Brown [13] [29] [31]
6Peter J. Camporese [1]
7Yuen H. Chan [1]
8Peter W. Cook [13]
9Brian W. Curran [1]
10Koushik K. Das [13] [16] [21]
11Jie Deng [24]
12James P. Eckhardt [1]
13S. K. H. Fung [10]
14F. H. Gebara [27]
15Amlan Ghosh [29] [31]
16Geng Han [34]
17Fook-Luen Heng [34]
18William V. Huott [1]
19Wei Hwang [5] [6] [7]
20Rajiv V. Joshi [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [22] [23] [25] [32]
21S. S. Kang [17]
22Rouwaida Kanj [25]
23Jae-Joon Kim [18] [22] [28] [29] [30] [33]
24Keunwoo Kim [11] [12] [16] [18] [19] [20] [22] [23] [24] [25] [26] [27] [30] [32]
25Daniel R. Knebel [1]
26S. Kowalczyk [8]
27K. Kroell [15]
28Jente B. Kuang [27]
29Barry P. Linder [8] [9]
30Shih-Hsien Lo [18] [21] [22]
31Salvatore Lombardo [8]
32Mark D. Mayo [1]
33A. Mocuta [17]
34Niladri Narayan Mojumder [28]
35Saibal Mukhopadhyay [18] [19] [20] [22] [26] [28] [30] [32] [33] [34]
36Hung C. Ngo [27]
37Gregory A. Northrop [8]
38Edward J. Nowak [23]
39Kevin J. Nowka [27]
40J. A. Pascual-Gutiérrez [17]
41Ruchir Puri [2] [3] [4] [11] [14]
42Rahul M. Rao [29] [31] [33]
43R. Rodríguez [8] [9]
44Kaushik Roy [18] [19] [20] [22] [28] [30]
45Ghavam V. Shahidi [5] [10]
46Melanie Sherony [10]
47Leon J. Sigal [1]
48Rama N. Singh [34]
49James H. Stathis [8] [9]
50James D. Warnock [1]
51Richard Q. Williams [23] [25]
52S. C. Wilson [5] [6]
53H.-S. Philip Wong [24]
54Philip T. Wu [1]
55I. Yang [10]
56N. Zamdmar [17]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)