Prashant Saxena

2006
26	EE	Prashant Saxena: The scaling of interconnect buffer needs. SLIP 2006: 109-112
25	EE	Rupesh S. Shelar, Prashant Saxena, Sachin S. Sapatnekar: Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 625-636 (2006)
24	EE	Prashant Saxena: On controlling perturbation due to repeaters during quadratic placement. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1733-1743 (2006)
2005
23	EE	Prashant Saxena, Kumar N. Lalgudi, Hans J. Greub, Janet Meiling Wang Roveda: A perturbation-aware noise convergence methodology for high frequency microprocessors. ASP-DAC 2005: 717-722
22	EE	Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar: Net weighting to reduce repeater counts during placement. DAC 2005: 503-508
21	EE	Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani: A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. ISCAS (6) 2005: 6230-6233
20	EE	Rupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar: An efficient technology mapping algorithm targeting routing congestion under delay constraints. ISPD 2005: 137-144
19	EE	Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang: A predictive distributed congestion metric with application to technology mapping. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 696-710 (2005)
2004
18	EE	Janet Meiling Wang, Prashant Saxena, Omar Hafiz, Xing Wang: Realizable parasitic reduction for distributed interconnects using matrix pencil technique. ASP-DAC 2004: 780-785
17	EE	Prashant Saxena, Bill Halpin: Modeling repeaters explicitly within analytical placement. DAC 2004: 699-704
16	EE	Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang: A predictive distributed congestion metric and its application to technology mapping. ISPD 2004: 210-217
15	EE	Desmond Kirkpatrick, Peter J. Osler, Louis Scheffer, Prashant Saxena, Dennis Sylvester: The great interconnect buffering debate: are you a chicken or an ostrich? ISPD 2004: 61
14	EE	Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick: Repeater scaling and its impact on CAD. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 451-463 (2004)
2003
13	EE	Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick: The scaling challenge: can correct-by-construction design help? ISPD 2003: 51-58
12	EE	Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang: Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. IEEE Trans. VLSI Syst. 11(5): 879-887 (2003)
11	EE	Prashant Saxena, Satyanarayan Gupta: On integrating power and signal routing for shield count minimization in congested regions. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 437-445 (2003)
2002
10	EE	B. Chappell, X. Wang, P. Patra, Prashant Saxena, J. Vendrell, Satyanarayan Gupta, S. Varadarajan, W. Gomes, S. Hussain, H. Krishnamurthy, M. Venkateshmurthy, S. Jain: A System-Level Solution to Domino Synthesis with 2 GHz Application. ICCD 2002: 164-
9	EE	Prashant Saxena, Satyanarayan Gupta: Shield count minimization in congested regions. ISPD 2002: 78-83
2001
8	EE	Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang: Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. DAC 2001: 732-737
7	EE	Prashant Saxena, C. L. Liu: Optimization of the maximum delay of global interconnects duringlayer assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 20(4): 503-515 (2001)
2000
6	EE	Prashant Saxena, C. L. Liu: A postprocessing algorithm for crosstalk-driven wire perturbation. IEEE Trans. on CAD of Integrated Circuits and Systems 19(6): 691-702 (2000)
1999
5	EE	Prashant Saxena, C. L. Liu: Crosstalk Minimization Using Wire Perturbations. DAC 1999: 100-103
4	EE	Prashant Saxena, Peichen Pan, C. L. Liu: The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. VLSI Design 1999: 402-407
1998
3	EE	Prashant Saxena, C. L. Liu: A performance-driven layer assignment algorithm for multiple interconnect trees. ICCAD 1998: 124-127
1996
2		Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu: A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. Euro-Par, Vol. I 1996: 828-831
1994
1		Aviezri S. Fraenkel, Edward M. Reingold, Prashant Saxena: Efficient Management of Dynamic Tables. Inf. Process. Lett. 50(1): 25-30 (1994)

Coauthor Index

1	Prithviraj Banerjee (Prith Banerjee)	[2]
2	Jinian Bian	[21]
3	Vamsi Boppana	[2]
4	Yici Cai	[21]
5	B. Chappell	[10]
6	Pasquale Cocchini	[13] [14]
7	Aviezri S. Fraenkel	[1]
8	W. Kent Fuchs	[2]
9	W. Gomes	[10]
10	Brent Goplen	[22]
11	Hans J. Greub	[23]
12	Satyanarayan Gupta	[9] [10] [11]
13	Omar Hafiz	[18]
14	Bill Halpin	[17]
15	Xianlong Hong	[21]
16	S. Hussain	[10]
17	S. Jain	[10]
18	Seong-Ook Jung	[8] [12]
19	S.-M. S. Kang	[12]
20	Sung-Mo Kang	[8]
21	Ki-Wook Kim	[8] [12]
22	Taewhan Kim	[12]
23	Desmond Kirkpatrick	[13] [14] [15]
24	H. Krishnamurthy	[10]
25	Kumar N. Lalgudi	[23]
26	Zhuoyuan Li	[21]
27	C. L. Liu (Chung Laung (Dave) Liu)	[2] [3] [4] [5] [6] [7] [8] [12]
28	Noel Menezes	[13] [14]
29	Peter J. Osler	[15]
30	Peichen Pan	[4]
31	P. Patra	[10]
32	Vijay Pitchumani	[21]
33	Edward M. Reingold	[1]
34	Sachin S. Sapatnekar	[16] [19] [20] [22] [25]
35	Louis Scheffer	[15]
36	Rupesh S. Shelar	[16] [19] [20] [25]
37	Dennis Sylvester	[15]
38	S. Varadarajan	[10]
39	J. Vendrell	[10]
40	M. Venkateshmurthy	[10]
41	Janet Meiling Wang (Janet Meiling Wang Roveda)	[18] [23]
42	X. Wang	[10]
43	Xing Wang	[18]
44	Xinning Wang	[16] [19] [20]
45	Hannal Yang	[21]
46	Qiang Zhou	[21]

Colors in the list of coauthors