Yehia Massoud

2009
62		Fabrizio Lombardi, Sanjukta Bhanja, Yehia Massoud, R. Iris Bahar: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009 ACM 2009
2008
61	EE	Arthur Nieuwoudt, Jamil Kawa, Yehia Massoud: Impact of dummy filling techniques on interconnect capacitance and planarization in nano-scale process technology. ACM Great Lakes Symposium on VLSI 2008: 151-154
60	EE	Hamid Nejati, Tamer Ragheb, Yehia Massoud: On the design of customizable low-voltage common-gate LNA-mixer pair using current and charge reusing techniques. ACM Great Lakes Symposium on VLSI 2008: 195-200
59	EE	Arthur Nieuwoudt, Jamil Kawa, Yehia Massoud: Automated design of tunable impedance matching networks for reconfigurable wireless applications. DAC 2008: 498-503
58	EE	Tamer Ragheb, Yehia Massoud: On the modeling of resistance in graphene nanoribbon (GNR) for future interconnect applications. ICCAD 2008: 593-597
57	EE	Arthur Nieuwoudt, Jamil Kawa, Yehia Massoud: Robust reconfigurable filter design using analytic variability quantification techniques. ICCAD 2008: 765-770
56	EE	Sami Kirolos, Yehia Massoud: Robust wide range of supply-voltage operation using continuous adaptive size-ratio gates. ISCAS 2008: 1232-1235
55	EE	Stephen Pfetsch, Tamer Ragheb, Jason N. Laska, Hamid Nejati, Anna C. Gilbert, Martin Strauss, Richard G. Baraniuk, Yehia Massoud: On the feasibility of hardware implementation of sub-Nyquist random-sampling based analog-to-information conversion. ISCAS 2008: 1480-1483
54	EE	Amir Hosseini, Hamid Nejati, Yehia Massoud: An Analytical model for characteristic impedance in nanostrip plasmonic waveguides. ISCAS 2008: 2346-2349
53	EE	Sami Kirolos, Yehia Massoud, Yehea I. Ismail: Power-supply-variation-aware timing analysis of synchronous systems. ISCAS 2008: 2418-2421
52	EE	Amir Hosseini, Tamer Ragheb, Yehia Massoud: A fault-aware dynamic routing algorithm for on-chip networks. ISCAS 2008: 2653-2656
51	EE	Sami Kirolos, Yehia Massoud, Yehea I. Ismail: Accurate analytical delay modeling of CMOS clock buffers considering power supply variations. ISCAS 2008: 3394-3397
50	EE	Yehia Massoud, Arthur Nieuwoudt: Performance analysis of optimized carbon nanotube interconnect. ISCAS 2008: 792-795
49	EE	Hamid Nejati, Tamer Ragheb, Yehia Massoud: Analytical modeling of common-gate low noise amplifiers. ISCAS 2008: 888-891
48	EE	Arthur Nieuwoudt, Yehia Massoud: Investigating the Design, Performance, and Reliability of Multi-Walled Carbon Nanotube Interconnect. ISQED 2008: 691-696
47	EE	Arthur Nieuwoudt, Jamil Kawa, Yehia Massoud: Investigating the Impact of Fill Metal on Crosstalk-Induced Delay and Noise. ISQED 2008: 724-729
46	EE	Mohamed El-Nozahi, Yehia Massoud: On the tapering Factor for Wide-Band Cascaded amplifiers. Journal of Circuits, Systems, and Computers 17(1): 67-75 (2008)
45	EE	Mosin Mondal, Yehia Massoud: Accurate Analytical Modeling of Frequency Dependent Loop Self-inductance. Journal of Circuits, Systems, and Computers 17(1): 77-93 (2008)
44	EE	Sami Kirolos, Yehia Massoud: Dynamic voltage Scaling Continuous Adaptive-Size Cell Design Technique. Journal of Circuits, Systems, and Computers 17(5): 871-883 (2008)
2007
43		Hai Zhou, Enrico Macii, Zhiyuan Yan, Yehia Massoud: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007 ACM 2007
42	EE	Arthur Nieuwoudt, Mehboob Alam, Yehia Massoud: Reduced-Order Wide-Band Interconnect Model Realization using Filter-Based Spline Interpolation. ASP-DAC 2007: 373-378
41	EE	Mehboob Alam, Arthur Nieuwoudt, Yehia Massoud: Frequency Selective Model Order Reduction via Spectral Zero Projection. ASP-DAC 2007: 379-383
40	EE	Arthur Nieuwoudt, Tamer Ragheb, Yehia Massoud: Hierarchical Optimization Methodology for Wideband Low Noise Amplifiers. ASP-DAC 2007: 68-73
39	EE	Arthur Nieuwoudt, Mosin Mondal, Yehia Massoud: Predicting the Performance and Reliability of Carbon Nanotube Bundles for On-Chip Interconnect. ASP-DAC 2007: 708-713
38	EE	Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud: Thermally robust clocking schemes for 3D integrated circuits. DATE 2007: 1206-1211
37	EE	Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen, Narayanan Vijaykrishnan, Yehia Massoud: Assessing carbon nanotube bundle interconnect for future FPGA architectures. DATE 2007: 307-312
36	EE	Jason N. Laska, Sami Kirolos, Marco F. Duarte, Tamer Ragheb, Richard G. Baraniuk, Yehia Massoud: Theory and Implementation of an Analog-to-Information Converter using Random Demodulation. ISCAS 2007: 1959-1962
35	EE	Amir Hosseini, Yehia Massoud: Subwavelength Plasmonic Bragg Reflector Structures for On-chip Optoelectronic Applications. ISCAS 2007: 2283-2286
34	EE	Hamid Nejati, Tamer Ragheb, Arthur Nieuwoudt, Yehia Massoud: Modeling and Design of Ultrawideband Low Noise Amplifiers with Generalized Impedance Matching Networks. ISCAS 2007: 2622-2625
33	EE	Yehia Massoud, Arthur Nieuwoudt, Tamer Ragheb: Variability-Aware Synthesis for Wideband Low Noise Amplifiers. ISCAS 2007: 3219-3222
32	EE	Mehboob Alam, Arthur Nieuwoudt, Yehia Massoud: Wavelet-Based Interpolation Point Selection for Multi-Shifted Arnoldi. ISCAS 2007: 653-656
31	EE	Mosin Mondal, Sami Kirolos, Yehia Massoud: Estimation of Capacitive Crosstalk-Induced Short-Circuit Energy. ISCAS 2007: 897-900
30	EE	Arthur Nieuwoudt, Yehia Massoud: Assessing the Implications of Process Variations on Future Carbon Nanotube Bundle Interconnect Solutions. ISQED 2007: 119-126
29	EE	Mehboob Alam, Arthur Nieuwoudt, Yehia Massoud: Wavelet-Based Passivity Preserving Model Order Reduction for Wideband Interconnect Characterization. ISQED 2007: 432-437
28	EE	Mosin Mondal, Kartik Mohanram, Yehia Massoud: Parameter-Variation-Aware Analysis for Noise Robustness. ISQED 2007: 655-659
27	EE	Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud: Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers. ISQED 2007: 67-72
26	EE	Arthur Nieuwoudt, Tamer Ragheb, Hamid Nejati, Yehia Massoud: Increasing Manufacturing Yield for Wideband RF CMOS LNAs in the Presence of Process Variations. ISQED 2007: 801-806
25	EE	Mosin Mondal, Tamer Ragheb, Xiang Wu, Adnan Aziz, Yehia Massoud: Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations. ISQED 2007: 873-878
24	EE	Arthur Nieuwoudt, Tamer Ragheb, Yehia Massoud: Systematic Design Optimization Methodology for Multi-Band CMOS Low Noise Amplifiers. ISVLSI 2007: 139-144
23	EE	Soumya Eachempati, Narayanan Vijaykrishnan, Arthur Nieuwoudt, Yehia Massoud: Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures. ISVLSI 2007: 516-517
22	EE	Xiang Wu, Tamer Ragheb, Adnan Aziz, Yehia Massoud: Implementing DSP Algorithms with On-Chip Networks. NOCS 2007: 307-316
21	EE	Mosin Mondal, Yehia Massoud: A Methodology for the Estimation of Capacitive Crosstalk-Induced Short-Circuit Energy. Journal of Circuits, Systems, and Computers 16(3): 455-465 (2007)
20	EE	Mehboob Alam, Arthur Nieuwoudt, Yehia Massoud: Efficient Multi-Shifted Arnoldi Projection Using Wavelet Transform. Journal of Circuits, Systems, and Computers 16(5): 699-709 (2007)
19	EE	Arthur Nieuwoudt, Tamer Ragheb, Yehia Massoud: Narrow-band low-noise amplifier synthesis for high-performance system-on-chip design. Microelectronics Journal 38(12): 1123-1134 (2007)
2006
18	EE	Tamer Ragheb, Arthur Nieuwoudt, Yehia Massoud: Efficient modeling of integrated narrow-band low noise amplifiers for design space exploration. ACM Great Lakes Symposium on VLSI 2006: 187-191
17	EE	Mohamed El-Nozahi, Yehia Massoud: An integrated circuit/behavioral simulation framework for continuous-time sigma-delta ADCs. ACM Great Lakes Symposium on VLSI 2006: 353-356
16	EE	Arthur Nieuwoudt, Tamer Ragheb, Yehia Massoud: SOC-NLNA: synthesis and optimization for fully integrated narrow-band CMOS low noise amplifiers. DAC 2006: 879-884
15	EE	Qing Su, Jamil Kawa, Charles Chiang, Yehia Massoud: Accurate modeling of substrate resistive coupling for floating substrates. ACM Trans. Design Autom. Electr. Syst. 11(1): 44-51 (2006)
14	EE	Mosin Mondal, Yehia Massoud: Accurate Loop Self Inductance Bound for Efficient Inductance Screening. IEEE Trans. VLSI Syst. 14(12): 1393-1397 (2006)
13	EE	Arthur Nieuwoudt, Yehia Massoud: Variability-Aware Multilevel Integrated Spiral Inductor Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2613-2625 (2006)
12	EE	Yehia Massoud, Arthur Nieuwoudt: Modeling and design challenges and solutions for carbon nanotube-based interconnect in future high performance integrated circuits. JETC 2(3): 155-196 (2006)
2005
11	EE	Arthur Nieuwoudt, Yehia Massoud: Multi-level approach for integrated spiral inductor optimization. DAC 2005: 648-651
10		Arthur Nieuwoudt, Yehia Massoud: Robust automated synthesis methodology for integrated spiral inductors with variability. ICCAD 2005: 502-507
9		Mosin Mondal, Yehia Massoud: Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductance. ICCAD 2005: 691-696
2003
8	EE	Soyoung Kim, Yehia Massoud, S. Simon Wong: On the Accuracy of Return Path Assumption for Loop Inductance Extraction for 0.1?m Technology and Beyond. ISQED 2003: 401-404
2002
7	EE	Yehia Massoud, Jacob White: Improving the generality of the fictitious magnetic charge approach to computing inductances in the presence of permeable materials. DAC 2002: 552-555
6	EE	Yehia Massoud, Jacob White: FastMag: a 3-D magnetostatic inductance extraction program for structures with permeable materials. ICCAD 2002: 478-484
5	EE	Yehia Massoud, Jacob K. White: Simulation and modeling of the effect of substrate conductivity on coupling inductance and circuit crosstalk. IEEE Trans. VLSI Syst. 10(3): 286-291 (2002)
4	EE	Yehia Massoud, Steve S. Majors, Jamil Kawa, Tareq Bustami, Don MacMillen, Jacob K. White: Managing on-chip inductive effects. IEEE Trans. VLSI Syst. 10(6): 789-798 (2002)
2001
3	EE	Yehia Massoud, Jamil Kawa, Don MacMillen, Jacob White: Modeling and Analysis of Differential Signaling for Minimizing Inductive Cross-Talk. DAC 2001: 804-809
1999
2	EE	Mattan Kamon, Nuno Alexandre Marques, Yehia Massoud, Luis Miguel Silveira, Jacob White: Interconnect Analysis: From 3-D Structures to Circuit Models. DAC 1999: 910-914
1998
1	EE	Yehia Massoud, Steve S. Majors, Tareq Bustami, Jacob White: Layout Techniques for Minimizing On-Chip Interconnect Self Inductance. DAC 1998: 566-571

Coauthor Index

1	Mehboob Alam	[20] [29] [32] [41] [42]
2	Adnan Aziz	[22] [25]
3	R. Iris Bahar	[62]
4	Richard G. Baraniuk	[36] [55]
5	Sanjukta Bhanja	[62]
6	Tareq Bustami	[1] [4]
7	Charles Chiang	[15]
8	Marco F. Duarte	[36]
9	Soumya Eachempati	[23] [37]
10	Mohamed El-Nozahi	[17] [46]
11	Aman Gayasen	[37]
12	Anna C. Gilbert	[55]
13	Amir Hosseini	[35] [52] [54]
14	Yehea I. Ismail	[51] [53]
15	Mattan Kamon	[2]
16	Jamil Kawa	[3] [4] [15] [47] [57] [59] [61]
17	Soyoung Kim	[8]
18	Sami Kirolos	[27] [31] [36] [38] [44] [51] [53] [56]
19	Jason N. Laska	[36] [55]
20	Greg M. Link	[27] [38]
21	Fabrizio Lombardi	[62]
22	Don MacMillen	[3] [4]
23	Enrico Macii	[43]
24	Steve S. Majors	[1] [4]
25	Nuno Alexandre Marques	[2]
26	Kartik Mohanram	[28]
27	Mosin Mondal	[9] [14] [21] [25] [27] [28] [31] [38] [39] [45]
28	Hamid Nejati	[26] [34] [49] [54] [55] [60]
29	Arthur Nieuwoudt	[10] [11] [12] [13] [16] [18] [19] [20] [23] [24] [26] [29] [30] [32] [33] [34] [37] [39] [40] [41] [42] [47] [48] [50] [57] [59] [61]
30	Stephen Pfetsch	[55]
31	Tamer Ragheb	[16] [18] [19] [22] [24] [25] [26] [27] [33] [34] [36] [38] [40] [49] [52] [55] [58] [60]
32	Andrew J. Ricketts	[27] [38]
33	Luis Miguel Silveira (L. Miguel Silveira)	[2]
34	Martin Strauss (Martin J. Strauss)	[55]
35	Qing Su	[15]
36	Narayanan Vijaykrishnan (Vijaykrishnan Narayanan)	[23] [27] [37] [38]
37	Jacob K. White (Jacob White)	[1] [2] [3] [4] [5] [6] [7]
38	S. Simon Wong	[8]
39	Xiang Wu	[22] [25]
40	Zhiyuan Yan	[43]
41	Hai Zhou	[43]

Colors in the list of coauthors