Roger Woods

Roger F. Woods

2009
46	EE	Jürgen Becker, Roger Woods, Peter M. Athanas, Fearghal Morgan: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings Springer 2009
2008
45		Roger F. Woods, Katherine Compton, Christos-Savvas Bouganis, Pedro C. Diniz: Reconfigurable Computing: Architectures, Tools and Applications, 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings Springer 2008
44	EE	Gaye Lightbody, Roger Woods: QR Recursive Least Squares IP Core Example. ECBS 2008: 369-374
43	EE	Stephen McKeown, Roger Woods, John McAllister: Power efficient DSP datapath configuration methodology for FPGA. FPL 2008: 515-518
42	EE	John McGlone, Alan Marshall, Roger Woods: A real-time flow monitor architecture encompassing on-demand monitoring functions. NOMS 2008: 871-874
41	EE	Scott Fischaber, John McAllister, Roger Woods: Memory-Centric Hardware Synthesis from Dataflow Models. SAMOS 2008: 197-206
40	EE	Roger F. Woods, John V. McCanny, John G. McWhirter: From Bit Level Systolic Arrays to HDTV Processor Chips. Signal Processing Systems 53(1-2): 35-49 (2008)
2007
39	EE	Gaye Lightbody, Roger Woods, Jonathan Francey: Soft IP core implementation of recursive least squares filter using only multplicative and additive operators. FPL 2007: 597-600
38	EE	Erdem Motuk, Roger Woods, Stefan Bilbao, John McAllister: Design Methodology for Real-Time FPGA-Based Sound Synthesis. IEEE Transactions on Signal Processing 55(12): 5833-5845 (2007)
37	EE	John McAllister, Roger Woods, Scott Fischaber, E. Malins: Rapid implementation and optimisation of DSP systems on FPGA-centric heterogeneous platforms. Journal of Systems Architecture 53(8): 511-523 (2007)
2006
36	EE	John V. McCanny, Roger F. Woods, John G. McWhirter: From Bit Level Systolic Arrays to HDTV Processor Chips. ASAP 2006: 159-162
35	EE	Scott Fischaber, John McAllister, Roger Woods, E. Malins: Muir Hardware Synthesis for Multimedia Applications. ESTImedia 2006: 101-106
34	EE	Shane O'Neill, Alan Marshall, Roger Woods: Providing Input-Output Throughput Guarantees in a Buffered Crossbar Switch. ISCC 2006: 725-730
33	EE	Ying Yi, Roger Woods: Hierarchical synthesis of complex DSP functions using IRIS. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 806-820 (2006)
32	EE	John McAllister, Roger Woods, Richard Walke, D. Reilly: Multidimensional DSP Core Synthesis for FPGA. VLSI Signal Processing 43(2-3): 207-221 (2006)
2005
31		Erdem Motuk, Roger Woods, Stefan Bilbao: FPGA-Based Hardware for Physical Modelling Sound Synthesis by Finite Difference Schemes. FPT 2005: 103-110
30		Scott Fischaber, R. Hasson, John McAllister, Roger Woods: FPGA Core Network Implementation and Optimization: A Case Study. FPT 2005: 319-320
29	EE	Shane O'Neill, Alan Marshall, Roger Woods: A Novel Packet Marking Function for Real-Time Interactive MPEG-4 Video Applications in a Differentiated Services Network. NETWORKING 2005: 1031-1042
28	EE	Brendan McAllister, Alan Marshall, Roger Woods: Programmable Network Functionality for Improved QoS of Interactive Video Traffic. Net-Con 2005: 283-296
27	EE	John McAllister, Roger Woods, D. Reilly, Scott Fischaber, R. Hasson: Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms. SAMOS 2005: 414-423
26	EE	Lok-Kee Ting, Roger Woods, C. F. N. Cowan: Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers. IEEE Trans. VLSI Syst. 13(1): 86-95 (2005)
25	EE	Ying Yi, Roger Woods, Lok-Kee Ting, C. F. N. Cowan: High Speed FPGA-Based Implementations of Delayed-LMS Filters. VLSI Signal Processing 39(1-2): 113-131 (2005)
2004
24	EE	John McAllister, Roger Woods, Richard Walke: Embedded Context Aware Hardware Component Generation for Dataflow System Exploration. SAMOS 2004: 254-263
23	EE	Roger Woods, Russell Tessier: Guest Editorial: Field Programmable Logic. VLSI Signal Processing 36(1): 5-6 (2004)
2003
22	EE	Richard H. Turner, Roger Woods: Design Flow for Efficient FPGA Reconfiguration. FPL 2003: 972-975
21	EE	Gaye Lightbody, Roger Woods, Richard Walke: Design of a parameterizable silicon intellectual property core for QR-based RLS filtering. IEEE Trans. VLSI Syst. 11(4): 659-678 (2003)
2002
20	EE	Tim Courtney, Richard H. Turner, Roger Woods: Mapping Multi-Mode Circuits to LUT-Based FPGA Using Embedded MUXes. FCCM 2002: 318-
19	EE	Richard H. Turner, Roger Woods, Tim Courtney: Multiplier-less Realization of a Poly-phase Filter Using LUT-based FPGAs. FPL 2002: 192-201
2001
18		Gordon J. Brebner, Roger Woods: Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings Springer 2001
17	EE	Lok-Kee Ting, Roger Woods, Colin Cowan: Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiver. FPL 2001: 367-376
16	EE	Jean-Paul Heron, Roger Woods, Sakir Sezer, Richard H. Turner: Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead. VLSI Signal Processing 28(1-2): 97-113 (2001)
2000
15	EE	Tim Courtney, Richard H. Turner, Roger Woods: An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal Processing. FCCM 2000: 341-343
14	EE	Tim Courtney, Richard H. Turner, Roger Woods: Multiplexer Based Reconfiguration for Virtex Multipliers. FPL 2000: 749-758
13	EE	Gaye Lightbody, Richard Walke, Roger Woods, John V. McCanny: Linear QR Architecture for a Single Chip Adaptive Beamformer. VLSI Signal Processing 24(1): 67-81 (2000)
1999
12	EE	Jean-Paul Heron, Roger Woods: Accelerating Run-Time Reconfiguration on FCCMs. FCCM 1999: 260-261
11	EE	Richard H. Turner, Roger Woods, Sakir Sezer, Jean-Paul Heron: A Virtual Hardware Handler for RTR Systems. FCCM 1999: 262-263
1998
10	EE	Sakir Sezer, Roger Woods, Jean-Paul Heron, Alan Marshall: Fast Partial Reconfiguration for FCCMs. FCCM 1998: 318-319
9	EE	Gareth Keane, Jonathan Spanier, Roger Woods: The impact of data characteristics and hardware topology on hardware selection for low power DSP. ISLPED 1998: 94-96
8	EE	Roger Woods, David W. Trainor, Jean-Paul Heron: Applying an XC6200 to Real-Time Image Processing. IEEE Design & Test of Computers 15(1): 30-38 (1998)
1997
7	EE	Roger Woods, Stefan H.-M. Ludwig, Jean-Paul Heron, David W. Trainor, Stephan W. Gehring: FPGA synthesis on the XC6200 using IRIS and Trianus/Hades (or from heaven to hell and back again). FCCM 1997: 155-164
6	EE	David W. Trainor, Roger F. Woods, John V. McCanny: Architectural Synthesis of Digital Signal Processing Algorithms Using "IRIS". VLSI Signal Processing 16(1): 41-55 (1997)
1996
5	EE	Colin C. W. Hui, Tiong Jiu Ding, John V. McCanny, Roger F. Woods: A New FFT Architecture and Chip Design for Motion Compensation based on Phase Correlation. ASAP 1996: 83-92
4		David W. Trainor, Roger Woods: Architectural Synthesis and Efficient Circuit Implementation for Field Programmable Gate Arrays. FPL 1996: 116-125
3		Jean-Paul Heron, Roger Woods: Architectural Strategies for Implementing an Image Processing Algorithm on XC6000 FPGA. FPL 1996: 317-326
1991
2		O. C. McNally, John V. McCanny, Roger F. Woods: Design of a Highly Pipelined 2nd Order IIR Filter Chip. VLSI 1991: 19-28
1989
1	EE	S. C. Knowles, John G. McWhirter, Roger F. Woods, John V. McCanny: Bit-Level systolic architectures for high performance IIR filtering. VLSI Signal Processing 1(1): 9-24 (1989)

Coauthor Index

1	Peter M. Athanas (Peter Athanas)	[46]
2	Jürgen Becker	[46]
3	Stefan Bilbao	[31] [38]
4	Christos-Savvas Bouganis	[45]
5	Gordon J. Brebner	[18]
6	Katherine Compton	[45]
7	Tim Courtney	[14] [15] [19] [20]
8	Colin Cowan (C. F. N. Cowan)	[17] [25] [26]
9	Tiong Jiu Ding	[5]
10	Pedro C. Diniz	[45]
11	Scott Fischaber	[27] [30] [35] [37] [41]
12	Jonathan Francey	[39]
13	Stephan W. Gehring	[7]
14	R. Hasson	[27] [30]
15	Jean-Paul Heron	[3] [7] [8] [10] [11] [12] [16]
16	Colin C. W. Hui	[5]
17	Gareth Keane	[9]
18	S. C. Knowles	[1]
19	Gaye Lightbody	[13] [21] [39] [44]
20	Stefan H.-M. Ludwig	[7]
21	E. Malins	[35] [37]
22	Alan Marshall	[10] [28] [29] [34] [42]
23	Brendan McAllister	[28]
24	John McAllister	[24] [27] [30] [32] [35] [37] [38] [41] [43]
25	John V. McCanny	[1] [2] [5] [6] [13] [36] [40]
26	John McGlone	[42]
27	Stephen McKeown	[43]
28	O. C. McNally	[2]
29	John G. McWhirter	[1] [36] [40]
30	Fearghal Morgan	[46]
31	Erdem Motuk	[31] [38]
32	Shane O'Neill	[29] [34]
33	D. Reilly	[27] [32]
34	Sakir Sezer	[10] [11] [16]
35	Jonathan Spanier	[9]
36	Russell Tessier	[23]
37	Lok-Kee Ting	[17] [25] [26]
38	David W. Trainor	[4] [6] [7] [8]
39	Richard H. Turner	[11] [14] [15] [16] [19] [20] [22]
40	Richard Walke	[13] [21] [24] [32]
41	Ying Yi	[25] [33]

Colors in the list of coauthors