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Luca Macchiarulo

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2007
33EEMario R. Casu, Luca Macchiarulo: Adaptive Latency-Insensitive Protocols. IEEE Design & Test of Computers 24(5): 442-452 (2007)
2006
32EESergio Tota, Mario R. Casu, Luca Macchiarulo: Implementation analysis of NoC: a MPSoC trace-driven approach. ACM Great Lakes Symposium on VLSI 2006: 204-209
31EEMario R. Casu, Luca Macchiarulo: Floorplanning With Wire Pipelining in Adaptive Communication Channels. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2996-3004 (2006)
2005
30EEMario R. Casu, Luca Macchiarulo: A New System Design Methodology for Wire Pipelined SoC. DATE 2005: 944-945
29EEMario R. Casu, Luca Macchiarulo: Floorplan assisted data rate enhancement through wire pipelining: a real assessment. ISPD 2005: 121-128
28EEMario R. Casu, Luca Macchiarulo: Throughput-driven floorplanning with wire pipelining. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 663-675 (2005)
2004
27EELuca Macchiarulo, Consolato F. Caccamo, Davide Pandini: A comparison between mask- and field-programmable routing structures on industrial FPGA architectures. ACM Great Lakes Symposium on VLSI 2004: 436-439
26EEMario R. Casu, Luca Macchiarulo: A new approach to latency insensitive design. DAC 2004: 576-581
25EEMario R. Casu, Luca Macchiarulo: Issues in Implementing Latency Insensitive Protocols. DATE 2004: 1390-1391
24EEMario R. Casu, Luca Macchiarulo: On-Chip Transparent Wire Pipelining. ICCD 2004: 160-167
23EEMario R. Casu, Luca Macchiarulo: Floorplanning for throughput. ISPD 2004: 62-69
22EELuca Macchiarulo, Shih-Min Shu, Malgorzata Marek-Sadowska: Pipelining Sequential Circuits with Wave Steering. IEEE Trans. Computers 53(9): 1205-1210 (2004)
2003
21EEAmit Singh, Arindam Mukherjee, Luca Macchiarulo, Malgorzata Marek-Sadowska: PITIA: an FPGA for throughput-intensive applications. IEEE Trans. VLSI Syst. 11(3): 354-363 (2003)
20EEPierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: New techniques for efficiently assessing reliability of SOCs. Microelectronics Journal 34(1): 53-61 (2003)
2002
19EEMonica Donno, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino: Enhanced clustered voltage scaling for low power. ACM Great Lakes Symposium on VLSI 2002: 18-23
18EELuca Macchiarulo, Enrico Macii, Massimo Poncino: Wire Placement for Crosstalk Energy Minimization in Address Buses. DATE 2002: 158-162
17EEPierluigi Civera, Luca Macchiarulo, Massimo Violante: A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis. DFT 2002: 31-39
16EELuca Benini, Luca Macchiarulo, Alberto Macii, Massimo Poncino: Layout-driven memory synthesis for embedded systems-on-chip. IEEE Trans. VLSI Syst. 10(2): 96-105 (2002)
15EEPierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits. J. Electronic Testing 18(3): 261-271 (2002)
2001
14EEPierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: FPGA-Based Fault Injection for Microprocessor Systems. Asian Test Symposium 2001: 304-
13EELuca Benini, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino: From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip. DAC 2001: 784-789
12EELuca Macchiarulo, Luca Benini, Enrico Macii: On-the-fly layout generation for PTL macrocells. DATE 2001: 546-551
11EEPierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits . DFT 2001: 250-258
10EEPierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits. FPL 2001: 493-502
9EEPierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Exploiting FPGA for Accelerating Fault Injection Experiments. IOLTW 2001: 9-13
8EELuca Macchiarulo, Enrico Macii, Massimo Poncino: Low-energy for deep-submicron address buses. ISLPED 2001: 176-181
2000
7EELuca Macchiarulo, Malgorzata Marek-Sadowska: Wave-steering one-hot encoded FSMs. DAC 2000: 357-360
6EELuca Macchiarulo, Shih-Ming Shu, Malgorzata Marek-Sadowska: Wave Steered FSMs. DATE 2000: 270-276
5EEAmit Singh, Luca Macchiarulo, Arindam Mukherjee, Malgorzata Marek-Sadowska: A novel high throughput reconfigurable FPGA architecture. FPGA 2000: 22-29
4EEElena Dubrova, Luca Macchiarulo: A Comment on 'Graph-Based Algorithm for Boolean Function Manipulation'. IEEE Trans. Computers 49(11): 1290-1292 (2000)
1999
3 Luca Macchiarulo, Pierluigi Civera: Functional Decomposition through Structural Analysis of Decision Diagrams - the Binary and Multiple-Valued Cases. VLSI Design 1999: 218-
1998
2EEY. Bellan, Mario Costa, Giancarlo Ferrigno, Fabrizio Lombardi, Luca Macchiarulo, Alfonso Montuori, Eros Pasero, Camilla Rigotti: Artificial Neural Networks for Motion Emulation in Virtual Environments. CAPTECH 1998: 83-99
1EELuca Macchiarulo, Pierluigi Civera: Ternary Decision Diagrams with Inverted Edges and Cofactoring - An Application to Discrete Neural Networks Synthesis. ISMVL 1998: 58-

Coauthor Index

1Y. Bellan [2]
2Luca Benini [12] [13] [16]
3Consolato F. Caccamo [27]
4Mario R. Casu [23] [24] [25] [26] [28] [29] [30] [31] [32] [33]
5Pierluigi Civera [1] [3] [9] [10] [11] [14] [15] [17] [20]
6Mario Costa [2]
7Monica Donno [19]
8Elena Dubrova [4]
9Giancarlo Ferrigno [2]
10Fabrizio Lombardi [2]
11Alberto Macii [13] [16] [19]
12Enrico Macii [8] [12] [13] [18] [19]
13Malgorzata Marek-Sadowska [5] [6] [7] [21] [22]
14Alfonso Montuori [2]
15Arindam Mukherjee [5] [21]
16Davide Pandini [27]
17Eros Pasero [2]
18Massimo Poncino [8] [13] [16] [18] [19]
19Maurizio Rebaudengo [9] [10] [11] [14] [15] [20]
20Matteo Sonza Reorda [9] [10] [11] [14] [15] [20]
21Camilla Rigotti [2]
22Shih-Min Shu [22]
23Shih-Ming Shu [6]
24Amit Singh [5] [21]
25Sergio Tota [32]
26Massimo Violante [9] [10] [11] [14] [15] [17] [20]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)