Alexa Doboli
List of publications from the DBLP Bibliography Server - FAQ
2008 | ||
---|---|---|
59 | EE | Ying Wei, Alex Doboli: Structural Macromodeling of Analog Circuits Through Model Decoupling and Transformation. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 712-725 (2008) |
2007 | ||
58 | EE | Sankalp S. Kallakuri, Alex Doboli, Simona Doboli, Dan Pescaru, Daniel Curiac: SoC Design Point Selection for Dynamic Adaptation under Continuously Varying Throughput Constraints. AHS 2007: 365-372 |
57 | EE | Pengbo Sun, Ying Wei, Alex Doboli: Flexibility-oriented design methodology for reconfigurable DeltaSigma modulators. DATE 2007: 415-420 |
56 | EE | Meng Wang, Alex Doboli, Thomas G. Robertazzi, Simona Doboli, Daniel Curiac: Towards Scalable Distributed Control of Unmanned Autonomous Vehicles. SACI 2007: 147-152 |
55 | EE | Sankalp S. Kallakuri, Alex Doboli, Eugene A. Feinberg: Buffer Insertion for Bridges and Optimal Buffer Sizing for Communication Sub-System of Systems-on-Chip CoRR abs/0710.4638: (2007) |
54 | EE | Sankalp S. Kallakuri, Alex Doboli: Customization of Arbitration Policies and Buffer Space Distribution Using Continuous-Time Markov Decision Processes. IEEE Trans. VLSI Syst. 15(2): 240-245 (2007) |
53 | EE | Ying Wei, Alex Doboli, Hua Tang: Systematic Methodology for Designing Reconfigurable DeltaSigma Modulator Topologies for Multimode Communication Systems. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 480-496 (2007) |
52 | EE | Sankalp Kallakuri, Alex Doboli, Simona Doboli: Applying stochastic modeling to bus arbitration for systems-on-chip. Integration 40(2): 183-191 (2007) |
51 | EE | Hui Zhang, Simona Doboli, Hua Tang, Alex Doboli: Compiled code simulation of analog and mixed-signal systems using piecewise linear modeling of nonlinear parameters: A case study for DeltaSigma modulator simulation. Integration 40(3): 193-208 (2007) |
2006 | ||
50 | EE | Ying Wei, Alex Doboli: Systematic development of nonlinear analog circuit macromodels through successive operator composition and nonlinear model decoupling. DAC 2006: 1023-1028 |
49 | EE | Hui Zhang, Yang Zhao, Alex Doboli: ALAMO: an improved alpha-space based methodology for modeling process parameter variations in analog circuits. DATE 2006: 156-161 |
48 | EE | Ying Wei, Hua Tang, Alex Doboli: Systematic methodology for designing reconfigurable Delta-Sigma modulator topologies for multimode communication systems. DATE 2006: 393-398 |
47 | EE | Ying Wei, Alex Doboli: Library of structural analog cell macromodels for design of continuous-time reconfigurable Delta Sigma modulators. ISCAS 2006 |
46 | EE | Hua Tang, Alex Doboli: High-level synthesis of /spl Delta//spl Sigma/ Modulator topologies optimized for complexity, sensitivity, and power consumption. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 597-607 (2006) |
45 | EE | Hua Tang, Hui Zhang, Alex Doboli: Refinement-based synthesis of continuous-time analog filters through successive domain pruning, plateau search, and adaptive sampling. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1421-1440 (2006) |
44 | EE | Nagu R. Dhanwada, Alex Doboli, Adrián Núñez-Aldana, Ranga Vemuri: Hierarchical constraint transformation based on genetic optimization for analog system synthesis. Integration 39(3): 267-290 (2006) |
2005 | ||
43 | EE | Yulei Weng, Alex Doboli: Digital cell macro-model with regular substrate template and EKV based MOSFET model. ACM Great Lakes Symposium on VLSI 2005: 172-175 |
42 | EE | Sankalp Kallakuri, Nattawut Thepayasuwan, Alex Doboli, Eugene A. Feinberg: A continuous time markov decision process based on-chip buffer allocation methodology. ACM Great Lakes Symposium on VLSI 2005: 345-348 |
41 | EE | Sankalp Kallakuri, Alex Doboli: Energy conscious online architecture adaptation for varying latency constraints in sensor network applications. CODES+ISSS 2005: 148-153 |
40 | EE | Ying Wei, Alex Doboli: Systematic development of analog circuit structural macromodels through behavioral model decoupling. DAC 2005: 57-62 |
39 | EE | Hua Tang, Ying Wei, Alex Doboli: MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumption. DATE 2005: 264-269 |
38 | EE | Sankalp Kallakuri, Alex Doboli, Eugene A. Feinberg: Buffer Insertion for Bridges and Optimal Buffer Sizing for Communication Sub-System of Systems-on-Chip. DATE 2005: 826-827 |
37 | EE | Sankalp Kallakuri, Nattawut Thepayasuwan, Alex Doboli, Simona Doboli: Communication subsystem synthesis and analysis tool using bus architecture generation and stochastic arbitration policies. ISCAS (2) 2005: 1044-1047 |
36 | EE | Hua Tang, Alex Doboli: Parameter domain pruning for improving convergence of synthesis algorithms. ISCAS (2) 2005: 1282-1285 |
35 | EE | Hui Zhang, Preethi Karthik, Hua Tang, Alex Doboli: An explorative tile-based technique for automated constraint transformation, placement and routing of high frequency analog filters. ISCAS (6) 2005: 5629-5632 |
34 | EE | Nattawut Thepayasuwan, Alex Doboli: Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed. IEEE Trans. VLSI Syst. 13(5): 525-538 (2005) |
2004 | ||
33 | EE | Nattawut Thepayasuwan, Alex Doboli: Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip. DATE 2004: 108-113 |
32 | Hui Zhang, Alex Doboli: SystemC Simulation of Continuous-Time $Sigma-Delta$ Analog-Digital Converters in the Presence of Non-linearities. FDL 2004: 32-44 | |
31 | EE | Nattawut Thepayasuwan, Alex Doboli: Hardware-Software Co-Design of Resource Constrained Systems on a Chip. ICDCS Workshops 2004: 818-823 |
30 | EE | Yulei Weng, Alex Doboli: Smart Sensor Architecture Customized for Image Processing Applications. IEEE Real-Time and Embedded Technology and Applications Symposium 2004: 396-403 |
29 | Hui Zhang, Alex Doboli: Fast time-domain symbolic simulation for synthesis of sigma-delta analog-digital converters. ISCAS (5) 2004: 125-128 | |
28 | EE | Sankalp Kallakuri, Alex Doboli, Simona Doboli: Stochastic Modeling Based Environment for Synthesis and Comparison of Bus Arbitration Policies. ISVLSI 2004: 199-206 |
27 | EE | Nattawut Thepayasuwan, Alex Doboli: OSIRIS: Automated Synthesis of Flat and Hierarchical Bus Architectures for Deep Submicron Systems on Chip. ISVLSI 2004: 264-265 |
26 | EE | Alex Doboli, Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri: A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications. ACM Trans. Design Autom. Electr. Syst. 9(2): 238-271 (2004) |
2003 | ||
25 | EE | Hua Tang, Hui Zhang, Alex Doboli: Synthesis of continuous-time filters and analog to digital converters by integrated constraint transformation, floorplanning and routing. ACM Great Lakes Symposium on VLSI 2003: 207-210 |
24 | EE | Simona Doboli, Gaurav Gothoskar, Alex Doboli: Extraction of Piecewise-Linear Analog Circuit Models from Trained Neural Networks Using Hidden Neuron Clustering. DATE 2003: 11098-11099 |
23 | EE | Alex Doboli, Hua Tang, Hui Zhang: Towards High-Level Synthesis of Analog and Mixed-Signal Systems from VHDL-AMS Specifications. FDL 2003: 133-141 |
22 | EE | Nattawut Thepayasuwan, Vaishali Damle, Alex Doboli: Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip. ICCD 2003: 126-133 |
21 | EE | Nattawut Thepayasuwan, Hua Tang, Alex Doboli: An exploration-based binding and scheduling technique for synthesis of digital blocks for mixed-signal applications. ISCAS (5) 2003: 629-632 |
20 | EE | Hua Tang, Hui Zhang, Alex Doboli: Layout-Aware Analog System Synthesis Based on Symbolic Layout Description and Combined Block Parameter Exploration, Placement and Global Routing. ISVLSI 2003: 266-271 |
19 | Sankalp Kallakuri, Alex Doboli, Simona Doboli: Applying Stochastic Modeling to Bus Arbitration for Network-On-Chip Systems. VLSI 2003: 261-265 | |
18 | EE | Alex Doboli, Ranga Vemuri: Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS. IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1504-1520 (2003) |
17 | EE | Alex Doboli, Ranga Vemuri: Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies. IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1556-1568 (2003) |
2002 | ||
16 | EE | Alex Doboli, Ranga Vemuri: A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems. DATE 2002: 760-769 |
15 | Hua Tang, Alex Doboli: Layout-Aware Synthesis Methodology for Analog Systems Based on Combined Block Sizing, Floorplanning and Global Routing. IWLS 2002: 41-44 | |
14 | Nattawut Thepayasuwan, Alex Doboli: A Methodology for Core Placement and Bus Synthesis under Time, Area and Energy Consumption Constraints. IWLS 2002: 57-60 | |
2001 | ||
13 | EE | Alex Doboli, Ranga Vemuri: Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise Constraints. DAC 2001: 629-634 |
12 | EE | Alex Doboli: Integrated hardware-software co-synthesis for design of embedded systems under power and latency constraints. DATE 2001: 612-619 |
11 | EE | Alex Doboli, Ranga Vemuri: A regularity-based hierarchical symbolic analysis method for large-scale analog networks. DATE 2001: 806 |
10 | EE | Alex Doboli, Ranga Vemuri: Hierarchical performance optimization for synthesis of linear analog systems. ISCAS (5) 2001: 431-434 |
2000 | ||
9 | EE | Petru Eles, Alex Doboli, Paul Pop, Zebo Peng: Scheduling with bus access optimization for distributed embedded systems. IEEE Trans. VLSI Syst. 8(5): 472-491 (2000) |
1999 | ||
8 | EE | Alex Doboli, Adrián Núñez-Aldana, Nagu R. Dhanwada, Sree Ganesan, Ranga Vemuri: Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration. DAC 1999: 951-957 |
7 | EE | Alex Doboli, Ranga Vemuri: A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems. DATE 1999: 338-345 |
6 | Alex Doboli, Ranga Vemuri: A Decomposition-based Symbolic Analysis Method for Analog Synthesis from Behavioral Specifications. VLSI 1999: 305-317 | |
1998 | ||
5 | EE | Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli, Paul Pop: Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems. DATE 1998: 132- |
4 | EE | Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli, Paul Pop: Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems. EUROMICRO 1998: 10168- |
1996 | ||
3 | EE | Petru Eles, Zebo Peng, Krzysztof Kuchcinski, Alex Doboli: Hardware/Software Partitioning with Iterative Improvement Heuristics. ISSS 1996: 71-76 |
1995 | ||
2 | EE | Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli: Timing constraint specification and synthesis in behavioral VHDL. EURO-DAC 1995: 452-457 |
1994 | ||
1 | EE | Petru Eles, Zebo Peng, Alexa Doboli: VHDL system-level specification and partitioning in a hardware/software co-synthesis environment. CODES 1994: 49-55 |
1 | Daniel Curiac (Daniel-Ioan Curiac) | [56] [58] |
2 | Vaishali Damle | [22] |
3 | Nagu R. Dhanwada | [8] [26] [44] |
4 | Simona Doboli | [19] [24] [28] [37] [51] [52] [56] [58] |
5 | Petru Eles | [1] [2] [3] [4] [5] [9] |
6 | Eugene A. Feinberg | [38] [42] [55] |
7 | Sree Ganesan | [8] |
8 | Gaurav Gothoskar | [24] |
9 | Sankalp S. Kallakuri (Sankalp Kallakuri) | [19] [28] [37] [38] [41] [42] [52] [54] [55] [58] |
10 | Preethi Karthik | [35] |
11 | Krzysztof Kuchcinski | [2] [3] [4] [5] |
12 | Adrián Núñez-Aldana | [8] [26] [44] |
13 | Zebo Peng | [1] [2] [3] [4] [5] [9] |
14 | Dan Pescaru | [58] |
15 | Paul Pop | [4] [5] [9] |
16 | Thomas G. Robertazzi | [56] |
17 | Pengbo Sun | [57] |
18 | Hua Tang | [15] [20] [21] [23] [25] [35] [36] [39] [45] [46] [48] [51] [53] |
19 | Nattawut Thepayasuwan | [14] [21] [22] [27] [31] [33] [34] [37] [42] |
20 | Ranga Vemuri | [6] [7] [8] [10] [11] [13] [16] [17] [18] [26] [44] |
21 | Meng Wang | [56] |
22 | Ying Wei | [39] [40] [47] [48] [50] [53] [57] [59] |
23 | Yulei Weng | [30] [43] |
24 | Hui Zhang | [20] [23] [25] [29] [32] [35] [45] [49] [51] |
25 | Yang Zhao | [49] |