dblp.uni-trier.dewww.uni-trier.de

Hushrav Mogal

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeer - CSB - Google - MSN - Yahoo

2009
8EEHushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan: Fast and Accurate Statistical Criticality Computation Under Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 350-363 (2009)
2008
7EEHushrav Mogal, Kia Bazargan: Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction. ICCAD 2008: 302-305
2007
6EEHushrav Mogal, Kia Bazargan: Microarchitecture floorplanning for sub-threshold leakage reduction. DATE 2007: 1238-1243
5EEHushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan: Clustering based pruning for statistical criticality computation under process variations. ICCAD 2007: 340-343
2006
4EECristinel Ababei, Hushrav Mogal, Kia Bazargan: Three-dimensional place and route for FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1132-1140 (2006)
2005
3EECristinel Ababei, Hushrav Mogal, Kia Bazargan: Three-dimensional place and route for FPGAs. ASP-DAC 2005: 773-778
2EECristinel Ababei, Hushrav Mogal, Kia Bazargan: 3D FPGAs: placement, routing, and architecture evaluation (abstract only). FPGA 2005: 263
1EECristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar: Placement and Routing in 3D Integrated Circuits. IEEE Design & Test of Computers 22(6): 520-531 (2005)

Coauthor Index

1Cristinel Ababei [1] [2] [3] [4]
2Kia Bazargan [1] [2] [3] [4] [5] [6] [7] [8]
3Yan Feng [1]
4Brent Goplen [1]
5Haifeng Qian [5] [8]
6Sachin S. Sapatnekar [1] [5] [8]
7Tianpei Zhang [1]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)