| 2009 |
|---|
| 8 | EE | Hushrav Mogal,
Haifeng Qian,
Sachin S. Sapatnekar,
Kia Bazargan:
Fast and Accurate Statistical Criticality Computation Under Process Variations.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 350-363 (2009) |
| 2008 |
|---|
| 7 | EE | Hushrav Mogal,
Kia Bazargan:
Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction.
ICCAD 2008: 302-305 |
| 2007 |
|---|
| 6 | EE | Hushrav Mogal,
Kia Bazargan:
Microarchitecture floorplanning for sub-threshold leakage reduction.
DATE 2007: 1238-1243 |
| 5 | EE | Hushrav Mogal,
Haifeng Qian,
Sachin S. Sapatnekar,
Kia Bazargan:
Clustering based pruning for statistical criticality computation under process variations.
ICCAD 2007: 340-343 |
| 2006 |
|---|
| 4 | EE | Cristinel Ababei,
Hushrav Mogal,
Kia Bazargan:
Three-dimensional place and route for FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1132-1140 (2006) |
| 2005 |
|---|
| 3 | EE | Cristinel Ababei,
Hushrav Mogal,
Kia Bazargan:
Three-dimensional place and route for FPGAs.
ASP-DAC 2005: 773-778 |
| 2 | EE | Cristinel Ababei,
Hushrav Mogal,
Kia Bazargan:
3D FPGAs: placement, routing, and architecture evaluation (abstract only).
FPGA 2005: 263 |
| 1 | EE | Cristinel Ababei,
Yan Feng,
Brent Goplen,
Hushrav Mogal,
Tianpei Zhang,
Kia Bazargan,
Sachin S. Sapatnekar:
Placement and Routing in 3D Integrated Circuits.
IEEE Design & Test of Computers 22(6): 520-531 (2005) |
