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Lawrence T. Pileggi

Larry T. Pileggi, Lawrence T. Pillage

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2009
151EESoner Yaldiz, Umut Arslan, Xin Li, Larry T. Pileggi: Efficient statistical analysis of read timing failures in SRAM circuits. ISQED 2009: 617-621
2008
150EEJason G. Brown, Brian Taylor, Ronald D. Blanton, Larry T. Pileggi: Automated Testability Enhancements for Logic Brick Libraries. DATE 2008: 480-485
149EEXin Li, Yaping Zhan, Lawrence T. Pileggi: Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 831-843 (2008)
148EEXin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi: Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1041-1054 (2008)
2007
147EEBrian Taylor, Larry T. Pileggi: Exact Combinatorial Optimization Methods for Physical Design of Regular Logic Bricks. DAC 2007: 344-349
146EEXin Li, Lawrence T. Pileggi: Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits. DAC 2007: 928-933
145EEJian Wang, Xin Li, Lawrence T. Pileggi: Parameterized Macromodeling for Analog System-Level Design Exploration. DAC 2007: 940-943
144EEXin Li, Brian Taylor, YuTsun Chien, Lawrence T. Pileggi: Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization. ICCAD 2007: 450-457
143EEPeng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif: Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction CoRR abs/0710.4654: (2007)
142EESounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi: Specification Test Compaction for Analog Circuits and MEMS CoRR abs/0710.4719: (2007)
141EEXin Li, Jiayong Le, Padmini Gopalakrishnan, Lawrence T. Pileggi: Asymptotic Probability Extraction for Nonnormal Performance Distributions. IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 16-37 (2007)
140EEXin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence T. Pileggi: Robust Analog/RF Circuit Design With Projection-Based Performance Modeling. IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 2-15 (2007)
2006
139EEXin Li, Jiayong Le, Lawrence T. Pileggi: Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions. DAC 2006: 103-108
138EEPadmini Gopalakrishnan, Xin Li, Lawrence T. Pileggi: Architecture-aware FPGA placement using metric embedding. DAC 2006: 460-465
137EEKim Yaw Tong, Lawrence T. Pileggi: Synthesis of Regular Logic Bricks for Robust IC Design. ICCD 2006
136EEXin Li, Jiayong Le, Lawrence T. Pileggi: Statistical Performance Modeling and Optimization. Foundations and Trends in Electronic Design Automation 1(4): (2006)
135EEPeng Li, Lawrence T. Pileggi, Mehdi Asheghi, Rajit Chandra: IC thermal simulation and modeling via efficient multigrid-based approaches. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1763-1776 (2006)
2005
134EEV. Kheterpal, V. Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, Andrzej J. Strojwas, Lawrence T. Pileggi: Design methodology for IC manufacturability based on regular logic-bricks. DAC 2005: 353-358
133EEYang Xu, Kan-Lin Hsiung, Xin Li, Ivan Nausieda, Stephen P. Boyd, Lawrence T. Pileggi: OPERA: optimization with ellipsoidal uncertainty for robust analog IC design. DAC 2005: 632-637
132EEYaping Zhan, Andrzej J. Strojwas, Xin Li, Lawrence T. Pileggi, David Newmark, Mahesh Sharma: Correlation-aware statistical timing analysis with non-gaussian delay distributions. DAC 2005: 77-82
131EESounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi: Specification Test Compaction for Analog Circuits and MEMS. DATE 2005: 164-169
130EEPeng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif: Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction. DATE 2005: 958-963
129 Xin Li, Jian Wang, Lawrence T. Pileggi, Tun-Shih Chen, Wanju Chiang: Performance-centering optimization for system-level analog design exploration. ICCAD 2005: 422-429
128 Xin Li, Jiayong Le, Lawrence T. Pileggi, Andrzej J. Strojwas: Projection-based performance modeling for inter/intra-die variations. ICCAD 2005: 721-727
127 Xin Li, Peng Li, Lawrence T. Pileggi: Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations. ICCAD 2005: 806-812
126 Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi: Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations. ICCAD 2005: 844-851
125EEPeng Li, Yangdong Deng, Lawrence T. Pileggi: Temperature-Dependent Optimization of Cache Leakage Power Dissipation. ICCD 2005: 7-12
124EEPeng Li, Lawrence T. Pileggi: Compact reduced-order modeling of weakly nonlinear analog and RF circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 184-203 (2005)
2004
123EEYang Xu, Lawrence T. Pileggi, Stephen P. Boyd: ORACLE: optimization with recourse of analog circuits including layout extraction. DAC 2004: 151-154
122EEV. Kheterpal, Andrzej J. Strojwas, Lawrence T. Pileggi: Routing architecture exploration for regular fabrics. DAC 2004: 204-207
121EEJiayong Le, Xin Li, Lawrence T. Pileggi: STAC: statistical timing analysis with correlation. DAC 2004: 343-348
120EESatrajit Gupta, Lawrence T. Pileggi: CHIME: coupled hierarchical inductance model evaluation. DAC 2004: 800-805
119EEXin Li, Yang Xu, Peng Li, Padmini Gopalakrishnan, Lawrence T. Pileggi: A frequency relaxation approach for analog/RF system-level simulation. DAC 2004: 842-847
118EEVikas Chandra, Anthony Xu, Herman Schmit, Lawrence T. Pileggi: An Interconnect Channel Design Methodology for High Performance Integrated Circuits. DATE 2004: 1138-1143
117EEAneesh Koorapaty, V. Kheterpal, Padmini Gopalakrishnan, M. Fu, Lawrence T. Pileggi: Exploring Logic Block Granularity for Regular Fabrics. DATE 2004: 468-473
116EEXin Li, Jiayong Le, Padmini Gopalakrishnan, Lawrence T. Pileggi: Asymptotic probability extraction for non-normal distributions of circuit performance. ICCAD 2004: 2-9
115EEVikas Chandra, Herman Schmit, Anthony Xu, Lawrence T. Pileggi: A power aware system level interconnect design methodology for latency-insensitive systems. ICCAD 2004: 275-282
114EEPeng Li, Lawrence T. Pileggi, Mehdi Asheghi, Rajit Chandra: Efficient full-chip thermal modeling and analysis. ICCAD 2004: 319-326
113EEPeng Li, Lawrence T. Pileggi: Efficient harmonic balance simulation using multi-level frequency decomposition. ICCAD 2004: 677-682
112EEXin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence T. Pileggi: Robust analog/RF circuit design with projection-based posynomial modeling. ICCAD 2004: 855-862
111EERadu Marculescu, Diana Marculescu, Larry T. Pileggi: Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems. ICCD 2004: 168-173
110EEMichael W. Beattie, Lawrence T. Pileggi: Parasitics extraction with multipole refinement. IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 288-292 (2004)
2003
109EEXiaoning Qi, Goetz Leonhardt, Daniel Flees, Xiao-Dong Yang, Sangwoo Kim, Stephan Mueller, Hendrik Mau, Lawrence T. Pileggi: A fast simulation approach for inductive effects of VLSI interconnects. ACM Great Lakes Symposium on VLSI 2003: 108-111
108EEDavide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas: Bounding the efforts on congestion optimization for physical synthesis. ACM Great Lakes Symposium on VLSI 2003: 7-10
107EEAbbas El Gamal, Ivo Bolsens, Andy Broom, Christopher Hamlin, Philippe Magarshack, Zvi Or-Bach, Lawrence T. Pileggi: Fast, cheap and under control: the next implementation fabric. DAC 2003: 354-355
106EEPeng Li, Lawrence T. Pileggi: NORM: compact model order reduction of weakly nonlinear systems. DAC 2003: 472-477
105EEXin Li, Peng Li, Yang Xu, Lawrence T. Pileggi: Analog and RF circuit macromodels for system-level analysis. DAC 2003: 478-483
104EELawrence T. Pileggi, Herman Schmit, Andrzej J. Strojwas, Padmini Gopalakrishnan, V. Kheterpal, Aneesh Koorapaty, Chetan Patel, V. Rovner, K. Y. Tong: Exploring regular fabrics to optimize the performance-cost trade-off. DAC 2003: 782-787
103EEYang Xu, Xin Li, Peng Li, Lawrence T. Pileggi: Noise Macromodel for Radio Frequency Integrated Circuits. DATE 2003: 10150-10155
102EEAneesh Koorapaty, Vikas Chandra, K. Y. Tong, Chetan Patel, Lawrence T. Pileggi, Herman Schmit: Heterogeneous Programmable Logic Block Architectures. DATE 2003: 11118-11119
101EEAneesh Koorapaty, Lawrence T. Pileggi, Herman Schmit: Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics. FPL 2003: 426-436
100EEPeng Li, Xin Li, Yang Xu, Lawrence T. Pileggi: A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits. ICCAD 2003: 454-462
99EEJiayong Le, Lawrence T. Pileggi, Anirudh Devgan: Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics. ICCAD 2003: 491-496
98EEChetan Patel, Anthony Cozzie, Herman Schmit, Lawrence T. Pileggi: An architectural exploration of via patterned gate arrays. ISPD 2003: 184-189
97EEE. Malley, A. Salinas, K. Ismail, Lawrence T. Pileggi: Power Comparison of Throughput Optimized IC Busses. ISVLSI 2003: 35-44
96EEHui Zheng, Byron Krauter, Lawrence T. Pileggi: Electrical Modeling of Integrated-Package Power and Ground Distributions. IEEE Design & Test of Computers 20(3): 24-31 (2003)
95EEPeng Li, Lawrence T. Pileggi: Efficient per-nonlinearity distortion analysis for analog and RF circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1297-1309 (2003)
94EEDavide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas: Global and local congestion optimization in technology mapping. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 498-505 (2003)
2002
93 Lawrence T. Pileggi, Andreas Kuehlmann: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002, San Jose, California, USA, November 10-14, 2002 ACM 2002
92EEHui Zheng, Lawrence T. Pileggi: Modeling and analysis of regular symmetrically structured power/ground distribution networks. DAC 2002: 395-398
91EETao Lin, Michael W. Beattie, Lawrence T. Pileggi: On the efficacy of simplified 2D on-chip inductance models. DAC 2002: 757-762
90EETao Lin, Michael W. Beattie, Lawrence T. Pileggi: On-Chip Inductance Models: 3D or Not 3D? DATE 2002: 1112
89EEEmrah Acar, Sani R. Nassif, Lawrence T. Pileggi: A Linear-Centric Simulation Framework for Parametric Fluctuations. DATE 2002: 568-575
88EEHui Zheng, Lawrence T. Pileggi, Michael W. Beattie, Byron Krauter: Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses. DATE 2002: 628-633
87EEPeng Li, Lawrence T. Pileggi: A Linear-Centric Modeling Approach to Harmonic Balance Analysis. DATE 2002: 634-639
86EEDavide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas: Congestion-Aware Logic Synthesis. DATE 2002: 664-671
85EEAneesh Koorapaty, Lawrence T. Pileggi: Modular, Fabric-Specific Synthesis for Programmable Architectures. FPL 2002: 132-141
84EETao Lin, Lawrence T. Pileggi: Throughput-driven IC communication fabric synthesis. ICCAD 2002: 274-279
83EEHui Zheng, Lawrence T. Pileggi: Robust and passive model order reduction for circuits containing susceptance elements. ICCAD 2002: 761-766
82EEDavide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas: Understanding and addressing the impact of wiring congestion during technology mapping. ISPD 2002: 131-136
81EEEmrah Acar, Sani R. Nassif, Ying Liu, Lawrence T. Pileggi: Time-Domain Simulation of Variational Interconnect Models. ISQED 2002: 419-424
80EEMichael W. Beattie, Lawrence T. Pileggi: On-chip induction modeling: basics and advanced methods. IEEE Trans. VLSI Syst. 10(6): 712-729 (2002)
79EEPadmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje: An analysis of the wire-load model uncertainty problem. IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 23-31 (2002)
78EEEmrah Acar, Florentin Dartu, Lawrence T. Pileggi: TETA: transistor-level waveform evaluation for timing analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 605-616 (2002)
2001
77EEMichael W. Beattie, Lawrence T. Pileggi: Inductance 101: Modeling and Extraction. DAC 2001: 323-328
76EEMichael W. Beattie, Lawrence T. Pileggi: Modeling Magnetic Coupling for On-Chip Interconnect. DAC 2001: 335-340
75EEYi-Chang Lu, Mustafa Celik, Tak Young, Lawrence T. Pileggi: Min/max On-Chip Inductance Models and Delay Metrics. DAC 2001: 341-346
74EERavishankar Arunachalam, Ronald D. Blanton, Lawrence T. Pileggi: False Coupling Interactions in Static Timing Analysis. DAC 2001: 726-731
73EEMichael W. Beattie, Lawrence T. Pileggi: Efficient inductance extraction via windowing. DATE 2001: 430-436
72EETao Lin, Lawrence T. Pileggi: RC(L) interconnect sizing with second order considerations via posynomial programming. ISPD 2001: 16-21
71EEPadmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje: Overcoming wireload model uncertainty during physical design. ISPD 2001: 182-189
70EEEmrah Acar, Lawrence T. Pileggi, Sani R. Nassif, Ying Liu: Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations. ISQED 2001: 431-436
69EEMichael W. Beattie, Byron Krauter, Lale Alatan, Lawrence T. Pileggi: Equipotential shells for efficient inductance extraction. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 70-79 (2001)
2000
68EEYing Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas: Impact of interconnect variations on the clock skew of a gigahertz microprocessor. DAC 2000: 168-171
67EERaul Camposano, Jacob Greidinger, Patrick Groeneveld, Michael Jackson, Lawrence T. Pileggi, Louis Scheffer: Design closure (panel session): hope or hype? DAC 2000: 176-177
66EERavishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi: TACO: timing analysis with coupling. DAC 2000: 266-269
65 Michael W. Beattie, Satrajit Gupta, Lawrence T. Pileggi: Hierarchical Interconnect Circuit Models. ICCAD 2000: 215-221
1999
64EEYing Liu, Lawrence T. Pileggi, Andrzej J. Strojwas: Model Order-Reduction of RC(L) Interconnect Including Variational Analysis. DAC 1999: 201-206
63EEMichael W. Beattie, Lawrence T. Pileggi: IC Analyses Including Extracted Inductance Models. DAC 1999: 915-920
62EEEmrah Acar, Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi: S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric. Great Lakes Symposium on VLSI 1999: 60-63
61EEAltan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi: Practical considerations for passive reduction of RLC circuits. ICCAD 1999: 214-220
60EEMichael W. Beattie, Lawrence T. Pileggi: Electromagnetic parasitic extraction via a multipole method with hierarchical refinement. ICCAD 1999: 437-444
59EEMustafa Celik, Lawrence T. Pileggi: Metrics and bounds for phase delay and signal attenuation in RC(L)clock trees. IEEE Trans. on CAD of Integrated Circuits and Systems 18(3): 293-300 (1999)
58EEMichael W. Beattie, Lawrence T. Pileggi: Error bounds for capacitance extraction via window techniques. IEEE Trans. on CAD of Integrated Circuits and Systems 18(3): 311-321 (1999)
1998
57EERony Kay, Lawrence T. Pileggi: PRIMO: Probability Interpretation of Moments for Delay Calculation. DAC 1998: 463-468
56EEYing Liu, Lawrence T. Pileggi, Andrzej J. Strojwas: ftd: An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models. DAC 1998: 469-472
55EEFlorentin Dartu, Lawrence T. Pileggi: TETA: Transistor-Level Engine for Timing Analysis. DAC 1998: 595-598
54EETao Lin, Emrah Acar, Lawrence T. Pileggi: h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response. ICCAD 1998: 19-25
53EEPaul D. Gross, Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi: Determination of worst-case aggressor alignment for delay calculation. ICCAD 1998: 212-219
52EELawrence T. Pileggi: Timing metrics for physical design of deep submicron technologies. ISPD 1998: 28-33
51EERohini Gupta, John Willis, Lawrence T. Pileggi: Analytic termination metrics for pin-to-pin lossy transmission lines with nonlinear drivers. IEEE Trans. VLSI Syst. 6(3): 457-463 (1998)
50EERony Kay, Lawrence T. Pileggi: EWA: efficient wiring-sizing algorithm for signal nets and clock nets. IEEE Trans. on CAD of Integrated Circuits and Systems 17(1): 40-49 (1998)
49EEAltan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi: PRIMA: passive reduced-order interconnect macromodeling algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 645-654 (1998)
1997
48EEMichael W. Beattie, Lawrence T. Pileggi: Bounds for BEM Capacitance Extraction. DAC 1997: 133-136
47EEZhijiang He, Mustafa Celik, Lawrence T. Pileggi: SPIE: Sparse Partial Inductance Extraction. DAC 1997: 137-140
46EEFlorentin Dartu, Lawrence T. Pileggi: Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling. DAC 1997: 46-51
45EEGary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar: A hierarchical decomposition methodology for multistage clock circuits. ICCAD 1997: 266-273
44EEAltan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi: PRIMA: passive reduced-order interconnect macromodeling algorithm. ICCAD 1997: 58-65
43 Ashih D. Mehta, Yao-Ping Chen, Noel Menezes, D. F. Wong, Lawrence T. Pileggi: Clustering and Load Balancing for Buffered Clock Tree Synthesis. ICCD 1997: 217-223
42 Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi: CMOS Gate Delay Models for General RLC Loading. ICCD 1997: 224-229
41EERony Kay, Gennady Bucheuv, Lawrence T. Pileggi: EWA: exact wiring-sizing algorithm. ISPD 1997: 178-185
40EERohini Gupta, Byron Krauter, Lawrence T. Pileggi: Transmission line synthesis via constrained multivariable optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 6-19 (1997)
39EERohini Gupta, Bogdan Tutuianu, Lawrence T. Pileggi: The Elmore delay as a bound for RC trees with generalized input signals. IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 95-104 (1997)
38EESatyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi: Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets. IEEE Trans. on CAD of Integrated Circuits and Systems 16(2): 210-215 (1997)
37EENoel Menezes, Ross Baldick, Lawrence T. Pileggi: A sequential quadratic programming approach to concurrent gate and wire sizing. IEEE Trans. on CAD of Integrated Circuits and Systems 16(8): 867-881 (1997)
1996
36EEByron Krauter, Yu Xia, E. Aykut Dengi, Lawrence T. Pileggi: A Sparse Image Method for BEM Capacitance Extraction. DAC 1996: 357-362
35EEFlorentin Dartu, Bogdan Tutuianu, Lawrence T. Pileggi: RC-Interconnect Macromodels for Timing Simulation. DAC 1996: 544-547
34EEBogdan Tutuianu, Florentin Dartu, Lawrence T. Pileggi: An Explicit RC-Circuit Delay Approximation Based on the First Three Moments of the Impulse Response. DAC 1996: 611-616
33EERohini Gupta, Byron Krauter, Lawrence T. Pileggi: On Moment-Based Metric for Optimal Termination of Transmission Line Interconnects. VLSI Design 1996: 150-155
32EERohini Gupta, Seok-Yoon Kim, Lawrence T. Pileggi: Domain characterization of transmission line models and analyses. IEEE Trans. on CAD of Integrated Circuits and Systems 15(2): 184-193 (1996)
31EEFlorentin Dartu, Noel Menezes, Lawrence T. Pileggi: Performance computation for precharacterized CMOS gates with RC loads. IEEE Trans. on CAD of Integrated Circuits and Systems 15(5): 544-553 (1996)
30EESatyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi: Post-processing of clock trees via wiresizing and buffering for robust design. IEEE Trans. on CAD of Integrated Circuits and Systems 15(6): 691-701 (1996)
1995
29EEByron Krauter, Rohini Gupta, John Willis, Lawrence T. Pileggi: Transmission Line Synthesis. DAC 1995: 358-363
28EERohini Gupta, Byron Krauter, Bogdan Tutuianu, John Willis, Lawrence T. Pileggi: The Elmore Delay as a Bound for RC Trees with Generalized Input Signals. DAC 1995: 364-369
27EENoel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi: Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization. DAC 1995: 690-695
26EERohini Gupta, Lawrence T. Pileggi: Constrained multivariable optimization of transmission lines with general topologies. ICCAD 1995: 130-137
25EENoel Menezes, Ross Baldick, Lawrence T. Pileggi: A sequential quadratic programming approach to concurrent gate and wire sizing. ICCAD 1995: 144-151
24EELawrence T. Pileggi: Coping with RC(L) interconnect design headaches. ICCAD 1995: 246-253
23EEByron Krauter, Lawrence T. Pileggi: Generating sparse partial inductance matrices with guaranteed stability. ICCAD 1995: 45-52
1994
22EEFlorentin Dartu, Noel Menezes, Jessica Qian, Lawrence T. Pillage: A Gate-Delay Model for high-Speed CMOS Circuits. DAC 1994: 576-580
21EERohini Gupta, Lawrence T. Pillage: OTTER: Optimal Termination of Transmission Lines Excluding Radiation. DAC 1994: 640-645
20 Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer: Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis. EDAC-ETC-EUROASIC 1994: 332-337
19EENoel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage: RC interconnect synthesis-a moment fitting approach. ICCAD 1994: 418-425
18 Rohini Gupta, Seok-Yoon Kim, Lawrence T. Pillage: Domain Characterization of Transmission Line Models for Efficient Simulation. ICCD 1994: 558-562
17EESeok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage: Time-domain macromodels for VLSI interconnect analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 13(10): 1257-1270 (1994)
16EEJessica Qian, Satyamurthy Pullela, Lawrence T. Pillage: Modeling the "Effective capacitance" for the RC interconnect of CMOS gates. IEEE Trans. on CAD of Integrated Circuits and Systems 13(12): 1526-1535 (1994)
15EEDemos F. Anastasakis, Nanda Gopal, Seok-Yoon Kim, Lawrence T. Pillage: Enhancing the stability of asymptotic waveform evaluation for digital interconnect circuit applications. IEEE Trans. on CAD of Integrated Circuits and Systems 13(6): 729-736 (1994)
14EECurtis L. Ratzlaff, Lawrence T. Pillage: RICE: rapid interconnect circuit evaluation using AWE. IEEE Trans. on CAD of Integrated Circuits and Systems 13(6): 763-776 (1994)
1993
13EESatyamurthy Pullela, Noel Menezes, Lawrence T. Pillage: Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization. DAC 1993: 165-170
12EEDah-Cherng Yuan, Lawrence T. Pillage, Joseph T. Rahmeh: Evaluation of Parts by Mixed-Level DC-Connected Components in Logic Simulation. DAC 1993: 367-372
11EES. Y. Kim, Emre Tuncer, Rohini Gupta, Byron Krauter, T. Savarino, Dean P. Neikirk, Lawrence T. Pillage: An efficient methodology for extraction and simulation of transmission lines for application specific electronic modules. ICCAD 1993: 58-65
1992
10EEDemos F. Anastasakis, Nanda Gopal, Seok-Yoon Kim, Lawrence T. Pillage: On the Stability of Moment-Matching Approximations in Asymptotic Waveform Evaluation. DAC 1992: 207-212
9EERonn B. Brashear, Douglas R. Holberg, M. Ray Mercer, Lawrence T. Pillage: ETA: electrical-level timing analysis. ICCAD 1992: 258-262
8EESeok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage: AWE macromodels of VLSI interconnect for circuit simulation. ICCAD 1992: 64-70
1991
7EECurtis L. Ratzlaff, Nanda Gopal, Lawrence T. Pillage: RICE: Rapid Interconnect Circuit Evaluator. DAC 1991: 555-560
6 Nanda Gopal, Dean P. Neikirk, Lawrence T. Pillage: Evaluating RC-Interconnect Using Moment-Matching Approximations. ICCAD 1991: 74-77
1990
5 Douglas R. Holberg, Santanu Dutta, Lawrence T. Pillage: DC Parameterized Piecewise-Function Transistor Models for Bipolar and MOS Logic Stage Delay Evaluation. ICCAD 1990: 546-549
4EELawrence T. Pillage, Ronald A. Rohrer: Asymptotic waveform evaluation for timing analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 9(4): 352-366 (1990)
1989
3EEXueqing Zhang, Lawrence T. Pillage, Ronald A. Rohrer: Efficient Final Placement Based on Nets-as-Points. DAC 1989: 578-581
2EELawrence T. Pillage, Xueqing Huang, Ronald A. Rohrer: AWEsim: Asymptotic Waveform Evaluation for Timing Analysis. DAC 1989: 634-637
1988
1EELawrence T. Pillage, Ronald A. Rohrer: A Quadratic Metric with a Simple Solution Scheme for Initial Placement. DAC 1988: 324-329

Coauthor Index

1Emrah Acar [54] [62] [70] [78] [81] [89]
2Lale Alatan [69]
3Demos F. Anastasakis [10] [15]
4Umut Arslan [151]
5Ravishankar Arunachalam [42] [53] [66] [74]
6Mehdi Asheghi [114] [135]
7Ross Baldick [25] [37]
8Michael W. Beattie [48] [58] [60] [63] [65] [69] [73] [76] [77] [80] [88] [90] [91] [110]
9Sounil Biswas [131] [142]
10R. D. (Shawn) Blanton (Ronald D. Blanton) [74] [131] [142] [150]
11Ivo Bolsens [107]
12Stephen P. Boyd [123] [133]
13Ronn B. Brashear [9] [20]
14Andy Broom [107]
15Jason G. Brown [150]
16Gennady Bucheuv [41]
17Raul Camposano [67]
18Mustafa Celik [44] [47] [49] [59] [61] [62] [75] [126] [148]
19Rajit Chandra [114] [135]
20Vikas Chandra [102] [115] [118]
21Tun-Shih Chen [129]
22Yao-Ping Chen [43]
23Wanju Chiang [129]
24YuTsun Chien [144]
25Anthony Cozzie [98]
26Florentin Dartu [19] [22] [31] [34] [35] [42] [46] [55] [78]
27Yangdong Deng [125]
28E. Aykut Dengi [36]
29Anirudh Devgan [99]
30Santanu Dutta [5]
31Gary Ellis [45]
32Daniel Flees [109]
33M. Fu [117]
34Abbas El Gamal (Abbas A. El Gamal) [107]
35Nanda Gopal [6] [7] [8] [10] [15] [17]
36Padmini Gopalakrishnan [71] [79] [104] [112] [116] [117] [119] [138] [140] [141]
37Jacob Greidinger [67]
38Patrick Groeneveld [67]
39Paul D. Gross [53]
40Rohini Gupta [11] [18] [21] [26] [28] [29] [32] [33] [39] [40] [51]
41Satrajit Gupta [65] [120]
42Christopher Hamlin [107]
43Zhijiang He [47]
44T. G. Hersan [134]
45Douglas R. Holberg [5] [9]
46Kan-Lin Hsiung [133]
47Xueqing Huang [2]
48K. Ismail [97]
49Michael Jackson [67]
50Rony Kay [41] [50] [57]
51V. Kheterpal [104] [117] [122] [134]
52S. Y. Kim [11]
53Sangwoo Kim [109]
54Seok-Yoon Kim [8] [10] [15] [17] [18] [32]
55Aneesh Koorapaty [85] [101] [102] [104] [117]
56Byron Krauter [11] [23] [28] [29] [33] [36] [40] [69] [88] [96]
57Andreas Kuehlmann [93]
58Jiayong Le [99] [116] [121] [126] [128] [136] [139] [141] [148]
59Goetz Leonhardt [109]
60Peng Li [87] [95] [100] [103] [105] [106] [113] [114] [119] [124] [125] [127] [130] [131] [135] [142] [143]
61Xin Li [100] [103] [105] [112] [116] [119] [121] [126] [127] [128] [129] [130] [132] [133] [136] [138] [139] [140] [141] [143] [144] [145] [146] [148] [149] [151]
62Tao Lin [54] [72] [84] [90] [91]
63Frank Liu [130] [143]
64Ying Liu [56] [64] [68] [70] [81]
65Yi-Chang Lu [75]
66Philippe Magarshack [107]
67E. Malley [97]
68Diana Marculescu [111]
69Radu Marculescu [111]
70Hendrik Mau [109]
71Ashih D. Mehta [43]
72Noel Menezes [13] [19] [20] [22] [25] [27] [30] [31] [37] [38] [43]
73M. Ray Mercer [9] [20]
74D. Motiani [134]
75Stephan Mueller [109]
76Sani R. Nassif [68] [70] [81] [89] [130] [143]
77Ivan Nausieda [133]
78Dean P. Neikirk [6] [11]
79David Newmark [132]
80Altan Odabasioglu [44] [49] [61] [62] [71] [79]
81Chanhee Oh [20]
82Zvi Or-Bach [107]
83Davide Pandini [82] [86] [94] [108]
84Chetan Patel [98] [102] [104]
85Satyamurthy Pullela [13] [16] [19] [27] [30] [38]
86Xiaoning Qi [109]
87Jessica Qian [16] [22]
88Joseph T. Rahmeh [12]
89Karthik Rajagopal [53] [66]
90Salil Raje [71] [79]
91Curtis L. Ratzlaff [7] [14]
92Ronald A. Rohrer [1] [2] [3] [4]
93V. Rovner [104] [134]
94Rob A. Rutenbar [45]
95A. Salinas [97]
96T. Savarino [11]
97Louis Scheffer [67]
98Herman Schmit [98] [101] [102] [104] [115] [118]
99Mahesh Sharma [132]
100Andrzej J. Strojwas [56] [64] [68] [82] [86] [94] [104] [108] [122] [128] [132] [134]
101Y. Takegawa [134]
102Brian Taylor [144] [147] [150]
103K. Y. Tong [102] [104]
104Kim Yaw Tong [137]
105Emre Tuncer [11]
106Bogdan Tutuianu [28] [34] [35] [39]
107Jian Wang [129] [145]
108John Willis [28] [29] [51]
109Martin D. F. Wong (D. F. Wong) [43]
110Yu Xia [36]
111Anthony Xu [115] [118]
112Yang Xu [100] [103] [105] [112] [119] [123] [133] [140]
113Soner Yaldiz [151]
114Xiao-Dong Yang [109]
115Tak Young [75]
116Dah-Cherng Yuan [12]
117Yaping Zhan [132] [149]
118Xueqing Zhang [3]
119Hui Zheng [83] [88] [92] [96]

Colors in the list of coauthors

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Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)