| 2008 |
|---|
| 93 | EE | Dimitris Bekiaris,
Kiamal Z. Pekmestzi,
Christos A. Papachristou:
A high-speed radix-4 multiplexer-based array multiplier.
ACM Great Lakes Symposium on VLSI 2008: 115-118 |
| 92 | EE | Francis G. Wolff,
Christos A. Papachristou,
Swarup Bhunia,
Rajat Subhra Chakraborty:
Towards Trojan-Free Trusted ICs: Problem Analysis and Detection Scheme.
DATE 2008: 1362-1365 |
| 91 | EE | Francis G. Wolff,
Christos A. Papachristou:
An Embedded Flash Memory Vault for Software Trojan Protection.
HOST 2008: 97-99 |
| 90 | EE | Gorn Tepvorachai,
Christos A. Papachristou:
Multi-label imbalanced data enrichment process in neural net classifier training.
IJCNN 2008: 1301-1307 |
| 2007 |
|---|
| 89 | EE | Gorn Tepvorachai,
Christos A. Papachristou:
A Configurable FIR Filter Scheme based on an Adaptive Multilayer Network Structure.
AHS 2007: 176-183 |
| 88 | EE | Gorn Tepvorachai,
Christos A. Papachristou:
Facial Image Associative Memory Model.
AHS 2007: 233-242 |
| 87 | EE | Balkaran S. Gill,
Christos A. Papachristou,
Francis G. Wolff:
Interactive presentation: A new asymmetric SRAM cell to reduce soft errors and leakage power in FPGA.
DATE 2007: 1460-1465 |
| 86 | EE | Osama Al-Khaleel,
Christos A. Papachristou,
Francis G. Wolff,
Kiamal Z. Pekmestzi:
An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding.
IOLTS 2007: 71-78 |
| 2006 |
|---|
| 85 | EE | Gorn Tepvorachai,
Christos A. Papachristou:
Self-Configurable Neural Network Processor for FIR Filter Applications.
AHS 2006: 114-121 |
| 84 | EE | Osama Al-Khaleel,
Christos A. Papachristou,
Frank Wolff,
Kiamal Z. Pekmestzi:
A Large Scale Adaptable Multiplier for Cryptographic Applications.
AHS 2006: 477-484 |
| 83 | EE | Balkaran S. Gill,
Christos A. Papachristou,
Francis G. Wolff:
Soft delay error analysis in logic circuits.
DATE 2006: 47-52 |
| 82 | EE | Christos A. Papachristou,
J. Weaver,
R. Vijayakumar,
Francis G. Wolff:
A Dynamic Reconfigurable Fabric for Platform SoCs.
FPL 2006: 1-4 |
| 81 | EE | Osama Al-Khaleel,
Christos A. Papachristou,
Frank Wolff,
Kiamal Z. Pekmestzi:
FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems.
ICCD 2006 |
| 80 | EE | Shih-yu Yang,
Christos A. Papachristou:
A method for detecting interconnect DSM defects in systems on chip.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 197-204 (2006) |
| 79 | EE | Hani Rizk,
Christos A. Papachristou,
Francis G. Wolff:
A Self Test Program Design Technique for Embedded DSP Cores.
J. Electronic Testing 22(1): 71-87 (2006) |
| 2005 |
|---|
| 78 | EE | Balkaran S. Gill,
Michael Nicolaidis,
Francis G. Wolff,
Christos A. Papachristou,
Steven L. Garverick:
An Efficient BICS Design for SEUs Detection and Correction in Semiconductor Memories.
DATE 2005: 592-597 |
| 77 | EE | Jianchun Li,
Christos A. Papachristou,
Raj Shekhar:
Accelerating mutual information-based 3D medical image registration with An FPGA computing platform (abstract only).
FPGA 2005: 279 |
| 76 | EE | Balkaran S. Gill,
Michael Nicolaidis,
Christos A. Papachristou:
Radiation Induced Single-Word Multiple-Bit Upsets Correction in SRAM.
IOLTS 2005: 266-271 |
| 2004 |
|---|
| 75 | EE | Francis G. Wolff,
Christos A. Papachristou,
David R. McIntyre:
Test Compression and Hardware Decompression for Scan-Based SoCs.
DATE 2004: 716-717 |
| 74 | EE | Hani Rizk,
Christos A. Papachristou,
Francis G. Wolff:
Designing Self Test Programs for Embedded DSP Cores.
DATE 2004: 816-823 |
| 73 | EE | Jianchun Li,
Christos A. Papachristou,
Raj Shekhar:
A Reconfigurable SoC Architecture and Caching Scheme for 3D Medical Image Processing.
FCCM 2004: 320-321 |
| 72 | | Jianchun Li,
Christos A. Papachristou,
Raj Shekhar:
A "Brick" Caching Scheme for 3D Medical Imaging.
ISBI 2004: 563-566 |
| 71 | EE | Balkaran S. Gill,
Christos A. Papachristou,
Francis G. Wolff:
Soft Delay Error Effects in CMOS Combinational Circuits.
VTS 2004: 325-334 |
| 2003 |
|---|
| 70 | EE | Michael J. Knieser,
Francis G. Wolff,
Christos A. Papachristou,
Daniel J. Weyer,
David R. McIntyre:
A Technique for High Ratio LZW Compression.
DATE 2003: 10116-10121 |
| 2002 |
|---|
| 69 | EE | Francis G. Wolff,
Christos A. Papachristou:
Multiscan-Based Test Compression and Hardware Decompression Using LZ77.
ITC 2002: 331-339 |
| 68 | EE | Mehrdad Nourani,
Christos A. Papachristou:
False path exclusion in delay analysis of RTL structures.
IEEE Trans. VLSI Syst. 10(1): 30-43 (2002) |
| 2001 |
|---|
| 67 | EE | Shih-yu Yang,
Christos A. Papachristou,
Massood Tabib-Azar:
Improving Bus Test Via IDDT and Boundary Scan.
DAC 2001: 307-312 |
| 66 | EE | Kelly A. Ockunzzi,
Christos A. Papachristou:
Test Strategies for BIST at the Algorithmic and Register-Transfer Levels.
DAC 2001: 65-70 |
| 65 | EE | Kelly A. Ockunzzi,
Christos A. Papachristou:
Breaking Correlation to Improve Testability.
VTS 2001: 75-81 |
| 64 | EE | Mehrdad Nourani,
Joan Carletta,
Christos A. Papachristou:
Integrated test of interacting controllers and datapaths.
ACM Trans. Design Autom. Electr. Syst. 6(3): 401-422 (2001) |
| 2000 |
|---|
| 63 | EE | Mehrdad Nourani,
Joan Carletta,
Christos A. Papachristou:
Synthesis-for-testability of controller-datapath pairs that use gated clocks.
DAC 2000: 613-618 |
| 62 | EE | Joan Carletta,
Christos A. Papachristou,
Mehrdad Nourani:
Detecting Undetectable Controller Faults Using Power Analysis.
DATE 2000: 723-728 |
| 61 | | Mehrdad Nourani,
Christos A. Papachristou:
An ILP formulation to optimize test access mechanism in system-on-chip testing.
ITC 2000: 902-910 |
| 60 | EE | Mehrdad Nourani,
Christos A. Papachristou:
Stability-based algorithms for high-level synthesis of digital ASICs.
IEEE Trans. VLSI Syst. 8(4): 431-435 (2000) |
| 1999 |
|---|
| 59 | EE | Francis G. Wolff,
Michael J. Knieser,
Daniel J. Weyer,
Christos A. Papachristou:
Using codesign techniques to support analog functionality.
CODES 1999: 79-84 |
| 58 | EE | Christos A. Papachristou,
F. Martin,
Mehrdad Nourani:
Microprocessor Based Testing for Core-Based System on Chip.
DAC 1999: 586-591 |
| 57 | EE | Joan Carletta,
Mehrdad Nourani,
Christos A. Papachristou:
Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs.
DATE 1999: 278-282 |
| 56 | EE | Christos A. Papachristou,
Yusuf Alzazeri:
A Method of Distributed Controller Design for RTL Circuits.
DATE 1999: 774-775 |
| 55 | | Christos A. Papachristou:
High Time for Higher Level BIST.
ITC 1999: 1117 |
| 54 | EE | Ken Batcher,
Christos A. Papachristou:
Instruction Randomization Self Test For Processor Cores.
VTS 1999: 34-40 |
| 53 | EE | Christos A. Papachristou,
Mehrdad Nourani,
Mark Spining:
A multiple clocking scheme for low-power RTL design.
IEEE Trans. VLSI Syst. 7(2): 266-276 (1999) |
| 52 | EE | Mehrdad Nourani,
Christos A. Papachristou:
Structural Fault Testing of Embedded Cores Using Pipelining.
J. Electronic Testing 15(1-2): 129-144 (1999) |
| 1998 |
|---|
| 51 | EE | Wei Zhao,
Christos A. Papachristou:
Testing DSP Cores Based on Self-Test Programs.
DATE 1998: 166-172 |
| 50 | EE | Mehrdad Nourani,
Christos A. Papachristou:
A Bypass Scheme for Core-Based System Fault Testing.
DATE 1998: 979-980 |
| 49 | EE | Mehrdad Nourani,
Christos A. Papachristou:
Parallelism in Structural Fault Testing of Embedded Cores.
VTS 1998: 15-21 |
| 48 | EE | Christos A. Papachristou,
Mikhail Baklashov,
Kowen Lai:
High-Level Test Synthesis for Behavioral and Structural Designs.
J. Electronic Testing 13(2): 167-188 (1998) |
| 47 | EE | Kelly A. Ockunzzi,
Christos A. Papachristou:
Testability Enhancement for Control-Flow Intensive Behaviors.
J. Electronic Testing 13(3): 239-257 (1998) |
| 1997 |
|---|
| 46 | EE | Kowen Lai,
Christos A. Papachristou,
Mikhail Baklashov:
BIST testability enhancement using high level test synthesis for behavioral and structural designs.
Asian Test Symposium 1997: 338-342 |
| 45 | EE | Mehrdad Nourani,
Joan Carletta,
Christos A. Papachristou:
A Scheme for Integrated Controller-Datapath Fault Testing.
DAC 1997: 546-551 |
| 44 | EE | Mehrdad Nourani,
Christos A. Papachristou:
Structural BIST insertion using behavioral test analysis.
ED&TC 1997: 64-68 |
| 43 | EE | Christos A. Papachristou,
Mikhail Baklashov:
A test synthesis technique using redundant register transfers.
ICCAD 1997: 414-420 |
| 42 | | Kowen Lai,
Christos A. Papachristou,
Mikhail Baklashov:
High Level Test Synthesis Across the Boundary of Behavioral and Structural Domains.
ICCD 1997: 636-641 |
| 41 | | Kelly A. Ockunzzi,
Christos A. Papachristou:
Testability Enhancement for Behavioral Descriptions Containing Conditional Statements.
ITC 1997: 236-245 |
| 40 | EE | Joan Carletta,
Christos A. Papachristou:
Behavioral Testability Insertion for Datapath/Controller Circuits.
J. Electronic Testing 11(1): 9-28 (1997) |
| 1996 |
|---|
| 39 | EE | Kowen Lai,
Christos A. Papachristou:
BIST Testability Enhancement of System Level Circuits : Experience with An Industrial Design.
Asian Test Symposium 1996: 219- |
| 38 | EE | Christos A. Papachristou,
Mark Spining,
Mehrdad Nourani:
An Effective Power Management Scheme for RTL Design Based on Multiple Clocks.
DAC 1996: 337-342 |
| 37 | EE | Ehat Ercanli,
Christos A. Papachristou:
A Register File and Scheduling Model for Application Specific Processor Synthesis.
DAC 1996: 35-40 |
| 36 | EE | Wei Zhao,
Christos A. Papachristou:
Synthesis of reusable DSP cores based on multiple behaviors.
ICCAD 1996: 103-108 |
| 35 | EE | J. El-Ziq,
Najmi T. Jarwala,
Niraj K. Jha,
Peter Marwedel,
Christos A. Papachristou,
Janusz Rajski,
John W. Sheppard:
Hardware-Software Co-Design for Test: It's the Last Straw!
VTS 1996: 506-507 |
| 1995 |
|---|
| 34 | EE | Wei Zhao,
Christos A. Papachristou:
Architectural partitioning of control memory for application specific programmable processors.
ICCAD 1995: 521-526 |
| 33 | EE | Joan Carletta,
Christos A. Papachristou:
Testability analysis and insertion for RTL circuits based on pseudorandom BIST.
ICCD 1995: 162-167 |
| 32 | EE | Christos A. Papachristou,
Mark Spining,
Mehrdad Nourani:
A multiple clocking scheme for low power RTL design.
ISLPD 1995: 27-32 |
| 31 | | Christos A. Papachristou,
Joan Carletta:
Test Synthesis in the Behavioral Domain.
ITC 1995: 693-702 |
| 30 | EE | Joan Carletta,
Christos A. Papachristou:
Structural constraints for circular self-test paths.
VTS 1995: 486-491 |
| 29 | EE | Wen-Ben Jone,
Christos A. Papachristou:
A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 374-384 (1995) |
| 1993 |
|---|
| 28 | EE | Mehrdad Nourani,
Christos A. Papachristou:
A Layout Estimation Algorithm for RTL Datapaths.
DAC 1993: 285-291 |
| 27 | EE | Christos A. Papachristou,
Haidar Harmanani,
Mehrdad Nourani:
An Approach for Redesigning in Data Path Synthesis.
DAC 1993: 419-423 |
| 26 | EE | Haidar Harmanani,
Christos A. Papachristou:
An improved method for RTL synthesis with testability tradeoffs.
ICCAD 1993: 30-35 |
| 25 | | Scott Chiu,
Christos A. Papachristou:
A Partial Scan Cost Estimation Method at the System Level.
ICCD 1993: 146-150 |
| 24 | EE | H. Fatih Ugurdag,
Christos A. Papachristou:
A VLIW architecture based on shifting register files.
MICRO 1993: 263-268 |
| 23 | | Christos A. Papachristou,
Venkata R. Immaneni:
Vertical Migration of Software Functions and Algorithms Using Enhanced Microsequencing.
IEEE Trans. Computers 42(1): 45-61 (1993) |
| 1992 |
|---|
| 22 | EE | Mehrdad Nourani,
Christos A. Papachristou:
Move Frame Scheduling and Mixed Scheduling-Allocation for the Automated Synthesis of Digital Systems.
DAC 1992: 99-105 |
| 21 | | H. Fatih Ugurdag,
Christos A. Papachristou:
ALMP: A Shifting Memory Architecture for Loop Pipelining.
ICCD 1992: 564-568 |
| 20 | EE | Michael J. Knieser,
Christos A. Papachristou:
Y-Pipe: a conditional branching scheme without pipeline delays.
MICRO 1992: 125-128 |
| 1991 |
|---|
| 19 | EE | Scott Chiu,
Christos A. Papachristou:
A Design for Testability Scheme with Applications to Data Path Synthesis.
DAC 1991: 271-277 |
| 18 | EE | Christos A. Papachristou,
Scott Chiu,
Haidar Harmanani:
A Data Path Synthesis Method for Self-Testable Designs.
DAC 1991: 378-384 |
| 17 | | Scott Chiu,
Christos A. Papachristou:
A Built-In Self-Testing Approach for Minimizing Hardware Overhead.
ICCD 1991: 282-285 |
| 16 | | Christos A. Papachristou,
Scott Chiu,
Haidar Harmanani:
SYNTEST: A Method for High-Level SYNthesis with Self-TESTability.
ICCD 1991: 458-462 |
| 1990 |
|---|
| 15 | EE | Christos A. Papachristou,
Haluk Konuk:
A Linear Program Driven Scheduling and Allocation Method Followed by an Interconnect Optimization Algorithm.
DAC 1990: 77-83 |
| 14 | EE | Jong-Jiann Shieh,
Christos A. Papachristou:
An instruction reoderer for pipelined computers.
MICRO 1990: 135-142 |
| 13 | EE | Djahida Smati,
Jerry Hwang,
Christos A. Papachristou:
SMDSS - a structured microcode development and simulation system.
MICRO 1990: 252-259 |
| 12 | EE | Christos A. Papachristou,
Anil L. Pandya:
A design scheme for PLA-based control tables with reduced area and time-delay cost.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(5): 453-472 (1990) |
| 1989 |
|---|
| 11 | EE | Wen-Ben Jone,
Christos A. Papachristou:
A Coordinated Approach to Partitioning and Test Pattern Generation for Pseudoexhaustive Testing.
DAC 1989: 525-534 |
| 10 | EE | Wen-Ben Jone,
Christos A. Papachristou,
M. Pereira:
A Scheme for Overlaying Concurrent Testing of VLSI Circuits.
DAC 1989: 531-536 |
| 9 | EE | Jong-Jiann Shieh,
Christos A. Papachristou:
On reordering instruction streams for pipelined computers.
MICRO 1989: 199-206 |
| 1988 |
|---|
| 8 | EE | L. Shih,
Christos A. Papachristou:
Mapping of micro data flow computations on parallel microarchitectures.
MICRO 1988: 70-72 |
| 1987 |
|---|
| 7 | | Christos A. Papachristou,
Suntae Hwang:
A Systolic Array Structure for Matrix Multiplication in the Residue Number System.
ICS 1987: 716-731 |
| 6 | EE | Christos A. Papachristou:
Associative table lookup processing for multioperand residue arithmetic.
J. ACM 34(2): 376-396 (1987) |
| 1986 |
|---|
| 5 | EE | Christos A. Papachristou:
Expert system approach to VLSI cell design (abstract).
ACM Conference on Computer Science 1986: 485 |
| 1985 |
|---|
| 4 | | Christos A. Papachristou,
Narendar B. Sahgal:
An Improved Method for Detecting Functional Faults in Semiconductor Random Access Memories.
IEEE Trans. Computers 34(2): 110-116 (1985) |
| 1983 |
|---|
| 3 | | Christos A. Papachristou:
Direct Implementation of Discrete and Residue-Based Functions Via Optimal Encoding: A Programmable Array Logic Approach.
IEEE Trans. Computers 32(10): 961-968 (1983) |
| 1978 |
|---|
| 2 | | Christos A. Papachristou:
An Algorithm for Optimal NAND Cascade Logic Synthesis.
IEEE Trans. Computers 27(12): 1099-1111 (1978) |
| 1977 |
|---|
| 1 | EE | Christos A. Papachristou:
Characteristic measures of switching functions.
Inf. Sci. 13(1): 51-75 (1977) |
