| 2009 |
|---|
| 97 | EE | Faizal Karim,
Marco Ottavi,
Hamidreza Hashempour,
Vamsi Vankamamidi,
Konrad Walus,
André Ivanov,
Fabrizio Lombardi:
Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits.
J. Electronic Testing 25(1): 55-66 (2009) |
| 2008 |
|---|
| 96 | EE | Partha Pratim Pande,
Amlan Ganguly,
Benjamin Belzer,
Alireza Nojeh,
André Ivanov:
Novel interconnect infrastructures for massive multicore chips - an overview.
ISCAS 2008: 2777-2780 |
| 2007 |
|---|
| 95 | EE | Marco Ottavi,
Hamid Hashempour,
Vamsi Vankamamidi,
Faizal Karim,
Konrad Walus,
André Ivanov:
On the Error Effects of Random Clock Shifts in Quantum-Dot Cellular Automata Circuits.
DFT 2007: 487-495 |
| 94 | EE | Cristian Grecu,
Lorena Anghel,
Partha Pratim Pande,
André Ivanov,
Resve Saleh:
Essential Fault-Tolerance Metrics for NoC Infrastructures.
IOLTS 2007: 37-42 |
| 93 | EE | Cristian Grecu,
André Ivanov,
Partha Pratim Pande,
Axel Jantsch,
Erno Salminen,
Ümit Y. Ogras,
Radu Marculescu:
Towards Open Network-on-Chip Benchmarks.
NOCS 2007: 205 |
| 92 | EE | Baosheng Wang,
Yuejian Wu,
André Ivanov:
A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs
CoRR abs/0710.4655: (2007) |
| 91 | EE | Cristian Grecu,
André Ivanov,
Resve A. Saleh,
Partha Pratim Pande:
Testing Network-on-Chip Communication Fabrics.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(12): 2201-2214 (2007) |
| 90 | EE | Zahra Sadat Ebadi,
Alireza Nasiri Avanaki,
Resve Saleh,
André Ivanov:
Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip.
Integration 40(2): 149-160 (2007) |
| 2006 |
|---|
| 89 | EE | Yuejian Wu,
André Ivanov:
Low Power SoC Memory BIST.
DFT 2006: 197-205 |
| 88 | EE | Cristian Grecu,
André Ivanov,
Res Saleh,
Partha Pratim Pande:
NoC Interconnect Yield Improvement Using Crosspoint Redundancy.
DFT 2006: 457-465 |
| 87 | EE | Cristian Grecu,
André Ivanov,
Res Saleh,
Egor S. Sogomonyan,
Partha Pratim Pande:
On-line Fault Detection and Location for NoC Interconnects.
IOLTS 2006: 145-150 |
| 86 | EE | Cristian Grecu,
Partha Pratim Pande,
André Ivanov,
Res Saleh:
BIST for Network-on-Chip Interconnect Infrastructures.
VTS 2006: 30-35 |
| 85 | EE | André Ivanov:
Session Abstract.
VTS 2006: 424-425 |
| 84 | EE | Josh Yang,
Baosheng Wang,
Yuejian Wu,
André Ivanov:
Fast detection of data retention faults and other SRAM cell open defects.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 167-180 (2006) |
| 2005 |
|---|
| 83 | EE | Baosheng Wang,
Josh Yang,
Yuejian Wu,
André Ivanov:
A retention-aware test power model for embedded SRAM.
ASP-DAC 2005: 1180-1183 |
| 82 | EE | Baosheng Wang,
Yuejian Wu,
André Ivanov:
A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs.
DATE 2005: 852-857 |
| 81 | EE | Cristian Grecu,
Partha Pratim Pande,
Baosheng Wang,
André Ivanov,
Res Saleh:
Methodologies and Algorithms for Testing Switch-Based NoC Interconnects.
DFT 2005: 238-246 |
| 80 | EE | Partha Pratim Pande,
Cristian Grecu,
Michael Jones,
André Ivanov,
Res Saleh:
Effect of traffic localization on energy dissipation in NoC-based interconnect.
ISCAS (2) 2005: 1774-1777 |
| 79 | EE | Samad Sheikhaei,
Shahriar Mirabbasi,
André Ivanov:
A 0.35µm CMOS comparator circuit for high-speed ADC applications.
ISCAS (6) 2005: 6134-6137 |
| 78 | EE | Samad Sheikhaei,
Shahriar Mirabbasi,
André Ivanov:
A 4-bit 5 GS/s flash A/D converter in 0.18µm CMOS.
ISCAS (6) 2005: 6138-6141 |
| 77 | EE | Baosheng Wang,
Yuejian Wu,
Josh Yang,
André Ivanov,
Yervant Zorian:
SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms.
VTS 2005: 66-71 |
| 76 | EE | André Ivanov,
Giovanni De Micheli:
Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research.
IEEE Design & Test of Computers 22(5): 399-403 (2005) |
| 75 | EE | Partha Pratim Pande,
Cristian Grecu,
André Ivanov,
Resve A. Saleh,
Giovanni De Micheli:
Design, Synthesis, and Test of Networks on Chips.
IEEE Design & Test of Computers 22(5): 404-413 (2005) |
| 74 | EE | Partha Pratim Pande,
Cristian Grecu,
Michael Jones,
André Ivanov,
Resve A. Saleh:
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures.
IEEE Trans. Computers 54(8): 1025-1040 (2005) |
| 73 | EE | Yvan Maidon,
Thomas Zimmer,
André Ivanov:
An Analog Circuit Fault Characterization Methodology.
J. Electronic Testing 21(2): 127-134 (2005) |
| 72 | EE | Baosheng Wang,
Andy Kuo,
Touraj Farahmand,
André Ivanov,
Yong B. Cho,
Sassan Tabatabaei:
A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices.
J. Electronic Testing 21(6): 621-630 (2005) |
| 71 | EE | Cristian Grecu,
Partha Pratim Pande,
André Ivanov,
Res Saleh:
Timing analysis of network on chip architectures for MP-SoC platforms.
Microelectronics Journal 36(9): 833-845 (2005) |
| 2004 |
|---|
| 70 | EE | Cristian Grecu,
Partha Pratim Pande,
André Ivanov,
Res Saleh:
Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs.
ACM Great Lakes Symposium on VLSI 2004: 192-195 |
| 69 | EE | Baosheng Wang,
Yuejian Wu,
André Ivanov:
Designs for Reducing Test Time of Distributed Small Embedded SRAMs.
DFT 2004: 120-128 |
| 68 | EE | Cristian Grecu,
Partha Pratim Pande,
André Ivanov,
Res Saleh:
A Scalable Communication-Centric SoC Interconnect Architecture.
ISQED 2004: 343-348 |
| 67 | EE | Andy Kuo,
Touraj Farahmand,
Nelson Ou,
André Ivanov,
Sassan Tabatabaei:
Jitter Models and Measurement Methods for High-Speed Serial Interconnects.
ITC 2004: 1295-1302 |
| 66 | EE | Josh Yang,
Baosheng Wang,
André Ivanov:
Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode.
VLSI Design 2004: 493-498 |
| 65 | EE | Josep Altet,
Antonio Rubio,
M. Amine Salhi,
J. L. Gálvez,
Stefan Dilhaire,
Ashish Syal,
André Ivanov:
Sensing temperature in CMOS circuits for Thermal Testing.
VTS 2004: 179-184 |
| 64 | EE | Baosheng Wang,
Josh Yang,
James Cicalo,
André Ivanov,
Yervant Zorian:
Reducing Embedded SRAM Test Time under Redundancy Constraints.
VTS 2004: 237-242 |
| 63 | EE | André Ivanov,
Fabrizio Lombardi,
Cecilia Metra:
Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates.
IEEE Design & Test of Computers 21(4): 274-276 (2004) |
| 62 | EE | Nelson Ou,
Touraj Farahmand,
Andy Kuo,
Sassan Tabatabaei,
André Ivanov:
Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects.
IEEE Design & Test of Computers 21(4): 302-313 (2004) |
| 61 | EE | Mohsen Nahvi,
André Ivanov:
Indirect test architecture for SoC testing.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1128-1142 (2004) |
| 2003 |
|---|
| 60 | EE | Baosheng Wang,
Yong B. Cho,
Sassan Tabatabaei,
André Ivanov:
Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing.
Asian Test Symposium 2003: 348-353 |
| 59 | EE | Zahra Sadat Ebadi,
André Ivanov:
Time Domain Multiplexed TAM: Implementation and Comparison.
DATE 2003: 10732-10737 |
| 58 | EE | Mama Hamour,
Resve A. Saleh,
Shahriar Mirabbasi,
André Ivanov:
Analog IP design flow for SoC applications.
ISCAS (4) 2003: 676-679 |
| 57 | EE | Partha Pratim Pande,
Cristian Grecu,
André Ivanov,
Res Saleh:
Design of a switch for network on chip applications.
ISCAS (5) 2003: 217-220 |
| 56 | EE | Partha Pratim Pande,
Cristian Grecu,
André Ivanov:
High-Throughput Switch-Based Interconnect for Future SoCs.
IWSOC 2003: 304-310 |
| 55 | EE | Baosheng Wang,
Josh Yang,
André Ivanov:
Reducing Test Time of Embedded SRAMs.
MTDT 2003: 47-52 |
| 54 | EE | Mohsen Nahvi,
André Ivanov:
An Embedded Autonomous Scan-Based Results Analyzer (EARA) for SoC Cores.
VTS 2003: 293-298 |
| 53 | EE | Florence Azaïs,
Yves Bertrand,
Michel Renovell,
André Ivanov,
Sassan Tabatabaei:
An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs.
IEEE Design & Test of Computers 20(1): 60-67 (2003) |
| 52 | EE | André Ivanov:
Test Technology Technical Council Newsletter.
J. Electronic Testing 19(1): 7-8 (2003) |
| 51 | EE | André Ivanov:
Guest Editorial.
J. Electronic Testing 19(2): 101-102 (2003) |
| 50 | EE | André Ivanov:
Test Technology Technical Council Newsletter.
J. Electronic Testing 19(2): 99-100 (2003) |
| 49 | EE | André Ivanov:
Test Technology Technical Council Newsletter.
J. Electronic Testing 19(3): 221-222 (2003) |
| 48 | EE | Josep Altet,
André Ivanov,
A. Wong:
Thermal Testing of Analogue Integrated Circuits: A Case Study.
J. Electronic Testing 19(3): 353-357 (2003) |
| 47 | EE | André Ivanov:
Test Technology Technical Council Newsletter.
J. Electronic Testing 19(4): 365-366 (2003) |
| 46 | EE | André Ivanov:
Test Technology Technical Council Newsletter.
J. Electronic Testing 19(5): 497-498 (2003) |
| 2002 |
|---|
| 45 | EE | B. Alorda,
André Ivanov,
Jaume Segura:
An Off-Chip Sensor Circuit for On-Line Transient Current Testing.
IOLTW 2002: 192 |
| 44 | EE | Mohsen Nahvi,
André Ivanov,
Resve A. Saleh:
Dedicated Autonomous Scan-Based Testing (DAST) for Embedded Cores.
ITC 2002: 1176-1184 |
| 43 | EE | Sassan Tabatabaei,
André Ivanov:
An Embedded Core for Sub-Picosecond Timing Measurements.
ITC 2002: 129-137 |
| 42 | EE | Sassan Tabatabaei,
André Ivanov:
Embedded Timing Analysis: A SoC Infrastructure.
IEEE Design & Test of Computers 19(3): 24-36 (2002) |
| 41 | EE | André Ivanov:
Test Technology Technical Council Newsletter.
J. Electronic Testing 18(2): 105-106 (2002) |
| 40 | EE | André Ivanov:
Test Technology Technical Council Newsletter.
J. Electronic Testing 18(3): 257-258 (2002) |
| 39 | EE | Ashish Syal,
Victor Lee,
André Ivanov,
Josep Altet:
CMOS Differential and Absolute Thermal Sensors.
J. Electronic Testing 18(3): 295-304 (2002) |
| 38 | EE | André Ivanov:
Test Technology Technical Council Newsletter.
J. Electronic Testing 18(4-5): 361-362 (2002) |
| 2001 |
|---|
| 37 | EE | Zahra Sadat Ebadi,
André Ivanov:
Design of an Optimal Test Access Architecture Using a Genetic Algorithm.
Asian Test Symposium 2001: 205- |
| 36 | EE | Ashish Syal,
Victor Lee,
André Ivanov,
Josep Altet:
CMOS Differential and Absolute Thermal Sensors.
IOLTW 2001: 127- |
| 35 | EE | André Ivanov,
Sumbal Rafiq,
Michel Renovell,
Florence Azaïs,
Yves Bertrand:
On the detectability of CMOS floating gate transistor faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 116-128 (2001) |
| 34 | EE | André Ivanov:
Test Technology Newsletter.
J. Electronic Testing 17(5): 369-370 (2001) |
| 2000 |
|---|
| 33 | EE | Bapiraju Vinnakota,
André Ivanov:
Biomedical ICs: What is Different about Testing those ICs?
VTS 2000: 329-332 |
| 32 | EE | Fidel Muradali,
André Ivanov:
Do I Need this Tool for My Chips to Work?
VTS 2000: 471-472 |
| 31 | EE | André Ivanov,
Vikram Devdas:
Catastrophic Short and Open Fault Detection in Bipolar CML Circuits: A Case Study.
J. Electronic Testing 16(6): 631-634 (2000) |
| 1999 |
|---|
| 30 | EE | Sassan Tabatabaei,
André Ivanov:
A built-in current monitor for testing analog circuit blocks.
ISCAS (2) 1999: 109-114 |
| 29 | | Michel Renovell,
André Ivanov,
Yves Bertrand,
Florence Azaïs,
Sumbal Rafiq:
Optimal conditions for Boolean and current detection of floating gate faults.
ITC 1999: 477-486 |
| 28 | EE | Sassan Tabatabaei,
André Ivanov:
A Current Integrator for BIST of Mixed-Signal ICs.
VTS 1999: 311-318 |
| 1998 |
|---|
| 27 | EE | Vikram Devdas,
André Ivanov:
Non-Intrusive Testing of High-Speed CML Circuits.
Asian Test Symposium 1998: 172-178 |
| 26 | EE | Sumbal Rafiq,
André Ivanov,
Sassan Tabatabaei,
Michel Renovell:
Testing for Floating Gates Defects in CMOS Circuits.
Asian Test Symposium 1998: 228-236 |
| 25 | EE | Florence Azaïs,
André Ivanov,
Michel Renovell,
Yves Bertrand:
A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs.
Asian Test Symposium 1998: 383-387 |
| 1997 |
|---|
| 24 | EE | Maneesha Dalmia,
André Ivanov,
Sassan Tabatabaei:
Power supply current monitoring techniques for testing PLLs.
Asian Test Symposium 1997: 366-371 |
| 1996 |
|---|
| 23 | | Yervant Zorian,
Tom Anderson,
Yvon Savaria,
Claude Thibeault,
André Ivanov:
Panel Summaries.
IEEE Design & Test of Computers 13(3): 6, 110-112 (1996) |
| 22 | | André Ivanov,
Barry K. Tsuji,
Yervant Zorian:
Programmable BIST Space Compactors.
IEEE Trans. Computers 45(12): 1393-1404 (1996) |
| 1995 |
|---|
| 21 | | Andrew Bishop,
André Ivanov:
Fault Simulation of an OTA Biquadratic Filter.
ISCAS 1995: 1764-1767 |
| 20 | EE | Yuejian Wu,
André Ivanov:
Reducing Hardware with Fuzzy Multiple Signature Analysis.
IEEE Design & Test of Computers 12(1): 68-74 (1995) |
| 19 | | Yuejian Wu,
André Ivanov:
Single-Reference Multiple Intermediate Signature (SREMIS) Analysis for BIST.
IEEE Trans. Computers 44(6): 817-825 (1995) |
| 18 | EE | D. Lambidonis,
André Ivanov,
Vinod K. Agarwal:
Fast signature computation for BIST linear compactors.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(8): 1037-1044 (1995) |
| 17 | EE | D. Lambidonis,
Vinod K. Agarwal,
André Ivanov,
Dhiren Xavier:
A quasi-optimal scheduling of intermediate signatures for multiple signature analysis compaction testing schemes.
J. Electronic Testing 6(1): 75-84 (1995) |
| 1994 |
|---|
| 16 | EE | A. J. Bishop,
André Ivanov:
On the Testability of CMOS Feedback Amplifiers.
DFT 1994: 65-73 |
| 15 | EE | Slawomir Pilarski,
André Ivanov,
Tiko Kameda:
On minimizing aliasing in scan-based compaction.
J. Electronic Testing 5(1): 83-90 (1994) |
| 1993 |
|---|
| 14 | | Yervant Zorian,
André Ivanov:
Programmable Space Compaction for BIST.
FTCS 1993: 340-349 |
| 13 | | Tiko Kameda,
Slawomir Pilarski,
André Ivanov:
Notes on Multiple Input Signature Analysis.
IEEE Trans. Computers 42(2): 228-234 (1993) |
| 12 | EE | Slawomir Pilarski,
Tiko Kameda,
André Ivanov:
Sequential faults and aliasing.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 1068-1074 (1993) |
| 1992 |
|---|
| 11 | | Yervant Zorian,
André Ivanov:
An Effective BIST Scheme for ROM's.
IEEE Trans. Computers 41(5): 646-653 (1992) |
| 10 | EE | Dhiren Xavier,
Robert C. Aitken,
André Ivanov,
Vinod K. Agarwal:
Using an asymmetric error model to study aliasing in signature analysis registers.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(1): 16-25 (1992) |
| 9 | EE | André Ivanov,
Yervant Zorian:
Count-based BIST compaction schemes and aliasing probability computation.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(6): 768-777 (1992) |
| 1991 |
|---|
| 8 | | D. Lambidonis,
André Ivanov,
Vinod K. Agarwal:
Fast Signature Computation for Linear Compactors.
ITC 1991: 808-817 |
| 7 | EE | André Ivanov,
Corot W. Starke,
Vinod K. Agarwal,
Wilfried Daehn,
Matthias Gruetzner,
Tom W. Williams:
Iterative algorithms for computing aliasing probabilities.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(2): 260-265 (1991) |
| 1990 |
|---|
| 6 | | André Ivanov,
Yervant Zorian:
Computing the Error Escape Probability in Count-Based Compaction Schemes.
ICCAD 1990: 368-371 |
| 1989 |
|---|
| 5 | | Dhiren Xavier,
Robert C. Aitken,
André Ivanov,
Vinod K. Agarwal:
: Experiments on Aliasing in Signature Analysis Registers.
ITC 1989: 344-354 |
| 4 | EE | André Ivanov,
Vinod K. Agarwal:
An analysis of the probabilistic behavior of linear feedback signature registers.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(10): 1074-1088 (1989) |
| 1988 |
|---|
| 3 | | Henry Cox,
André Ivanov,
Vinod K. Agarwal,
Janusz Rajski:
On Multiple Fault Coverage and Aliasing Probability Measures.
ITC 1988: 314-321 |
| 2 | EE | André Ivanov,
Vinod K. Agarwal:
Dynamic testability measures for ATPG.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(5): 598-608 (1988) |
| 1986 |
|---|
| 1 | | André Ivanov,
Vinod K. Agarwal:
Testability Measures : What Do They Do for ATPG ?
ITC 1986: 129-139 |
