| 2009 |
|---|
| 12 | EE | Shih-Hsu Huang,
Chia-Ming Chang,
Yow-Tyng Nieh:
Opposite-phase register switching for peak current minimization.
ACM Trans. Design Autom. Electr. Syst. 14(1): (2009) |
| 2007 |
|---|
| 11 | EE | Shih-Hsu Huang,
Chun-Hua Cheng,
Chia-Ming Chang,
Yow-Tyng Nieh:
Clock Period Minimization with Minimum Delay Insertion.
DAC 2007: 970-975 |
| 10 | EE | Shih-Hsu Huang,
Yow-Tyng Nieh:
Clock skew scheduling with race conditions considered.
ACM Trans. Design Autom. Electr. Syst. 12(4): (2007) |
| 9 | EE | Yow-Tyng Nieh,
Shih-Hsu Huang,
Sheng-Yu Hsu:
Opposite-Phase Clock Tree for Peak Current Reduction.
IEICE Transactions 90-A(12): 2727-2735 (2007) |
| 8 | EE | Shih-Hsu Huang,
Chia-Ming Chang,
Yow-Tyng Nieh:
A Fast Register Scheduling Approach to the Architecture of Multiple Clocking Domains.
J. Inf. Sci. Eng. 23(6): 1681-1705 (2007) |
| 2006 |
|---|
| 7 | EE | Shih-Hsu Huang,
Chia-Ming Chang,
Yow-Tyng Nieh:
Fast multi-domain clock skew scheduling for peak current reduction.
ASP-DAC 2006: 254-259 |
| 6 | EE | Shih-Hsu Huang,
Chun-Hua Cheng,
Yow-Tyng Nieh,
Wei-Chieh Yu:
Register binding for clock period minimization.
DAC 2006: 439-444 |
| 5 | EE | Shih-Hsu Huang,
Chia-Ming Chang,
Yow-Tyng Nieh:
State re-encoding for peak current minimization.
ICCAD 2006: 33-38 |
| 4 | EE | Shih-Hsu Huang,
Yow-Tyng Nieh:
Synthesis of nonzero clock skew circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 961-976 (2006) |
| 2005 |
|---|
| 3 | EE | Yow-Tyng Nieh,
Shih-Hsu Huang,
Sheng-Yu Hsu:
Minimizing peak current via opposite-phase clock tree.
DAC 2005: 182-185 |
| 2 | EE | Shih-Hsu Huang,
Yow-Tyng Nieh,
Feng-Pin Lu:
Race-condition-aware clock skew scheduling.
DAC 2005: 475-478 |
| 2003 |
|---|
| 1 | EE | Shih-Hsu Huang,
Yow-Tyng Nieh:
Clock Period Minimization of Non-Zero Clock Skew Circuits.
ICCAD 2003: 809-812 |
