2008 |
22 | EE | Hua Tang,
Li-Nang Xing:
A Web-Based Data Mining System for Forest Resource Planning System.
FSKD (4) 2008: 399-403 |
21 | EE | Hairong Chang,
Hua Tang:
A simple technique to reduce clock jitter effects in continuous-time delta-sigma modulators.
ISCAS 2008: 1870-1873 |
20 | EE | Hua Tang:
Post-optimization of Delta-Sigma modulators considering circuit non-idealities.
ISCAS 2008: 2546-2549 |
19 | EE | Matthew Webb,
Hua Tang:
Analog design retargeting by design knowledge reuse and circuit synthesis.
ISCAS 2008: 892-895 |
2007 |
18 | EE | Hua Tang:
Hierarchical statistical analysis of performance variation for continuous-time delta-sigma modulators.
VLSI-SoC 2007: 37-41 |
17 | EE | Ying Wei,
Alex Doboli,
Hua Tang:
Systematic Methodology for Designing Reconfigurable DeltaSigma Modulator Topologies for Multimode Communication Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 480-496 (2007) |
16 | EE | Hui Zhang,
Simona Doboli,
Hua Tang,
Alex Doboli:
Compiled code simulation of analog and mixed-signal systems using piecewise linear modeling of nonlinear parameters: A case study for DeltaSigma modulator simulation.
Integration 40(3): 193-208 (2007) |
15 | EE | Robert A. Morris,
Jacob K. Asiedu,
William A. Haber,
Fred SaintOurs,
Robert D. Stevenson,
Hua Tang:
Database-backed decision trees with application to biological informatics.
J. Intell. Inf. Syst. 29(1): 25-38 (2007) |
2006 |
14 | EE | Ying Wei,
Hua Tang,
Alex Doboli:
Systematic methodology for designing reconfigurable Delta-Sigma modulator topologies for multimode communication systems.
DATE 2006: 393-398 |
13 | EE | Pei Wang,
Hua Tang,
Heidi Zhang,
Jeffrey Whiteaker,
Amanda G. Paulovich,
Martin McIntosh:
Normalization Regarding Non-Random Missing Values in High-Throughput Mass Spectrometry Data.
Pacific Symposium on Biocomputing 2006: 315-326 |
12 | EE | Hua Tang,
Alex Doboli:
High-level synthesis of /spl Delta//spl Sigma/ Modulator topologies optimized for complexity, sensitivity, and power consumption.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 597-607 (2006) |
11 | EE | Hua Tang,
Hui Zhang,
Alex Doboli:
Refinement-based synthesis of continuous-time analog filters through successive domain pruning, plateau search, and adaptive sampling.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1421-1440 (2006) |
2005 |
10 | EE | Yong-Bing Shi,
Yin-Cai Tang,
Hua Tang,
Ling-Liu Gong,
Li Xu:
Two Classes of Simple MCD Graphs.
CJCDGCGT 2005: 177-188 |
9 | EE | Hua Tang,
Ying Wei,
Alex Doboli:
MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumption.
DATE 2005: 264-269 |
8 | EE | Hua Tang,
Alex Doboli:
Parameter domain pruning for improving convergence of synthesis algorithms.
ISCAS (2) 2005: 1282-1285 |
7 | EE | Hui Zhang,
Preethi Karthik,
Hua Tang,
Alex Doboli:
An explorative tile-based technique for automated constraint transformation, placement and routing of high frequency analog filters.
ISCAS (6) 2005: 5629-5632 |
2004 |
6 | EE | Piyush Maheshwari,
Hua Tang,
Roger Liang:
Enhancing Web Services with Message-Oriented Middleware.
ICWS 2004: 524-531 |
2003 |
5 | EE | Hua Tang,
Hui Zhang,
Alex Doboli:
Synthesis of continuous-time filters and analog to digital converters by integrated constraint transformation, floorplanning and routing.
ACM Great Lakes Symposium on VLSI 2003: 207-210 |
4 | EE | Alex Doboli,
Hua Tang,
Hui Zhang:
Towards High-Level Synthesis of Analog and Mixed-Signal Systems from VHDL-AMS Specifications.
FDL 2003: 133-141 |
3 | EE | Nattawut Thepayasuwan,
Hua Tang,
Alex Doboli:
An exploration-based binding and scheduling technique for synthesis of digital blocks for mixed-signal applications.
ISCAS (5) 2003: 629-632 |
2 | EE | Hua Tang,
Hui Zhang,
Alex Doboli:
Layout-Aware Analog System Synthesis Based on Symbolic Layout Description and Combined Block Parameter Exploration, Placement and Global Routing.
ISVLSI 2003: 266-271 |
2002 |
1 | | Hua Tang,
Alex Doboli:
Layout-Aware Synthesis Methodology for Analog Systems Based on Combined Block Sizing, Floorplanning and Global Routing.
IWLS 2002: 41-44 |