2009 |
45 | EE | Deming Chen,
Russell Tessier,
Mojy C. Chian,
Steve Trimberger,
Shinobu Fujita,
André DeHon,
Deming Chen:
CMOS vs Nano: comrades or rivals?
FPGA 2009: 121-122 |
2007 |
44 | | Romain Vaslin,
Guy Gogniat,
Jean-Philippe Diguet,
Russell Tessier,
Wayne Burleson:
High-efficiency protection solution for off-chip memory in embedded systems.
ERSA 2007: 117-123 |
43 | EE | Thomas Eisenbarth,
Tim Güneysu,
Christof Paar,
Ahmad-Reza Sadeghi,
Marko Wolf,
Russell Tessier:
Establishing Chain of Trust in Reconfigurable Hardware.
FCCM 2007: 289-290 |
42 | EE | Kevin Oo Tinmaung,
David Howland,
Russell Tessier:
Power-aware FPGA logic synthesis using binary decision diagrams.
FPGA 2007: 148-155 |
41 | EE | Weifeng Xu,
Russell Tessier:
Tetris: a new register pressure control technique for VLIW processors.
LCTES 2007: 113-122 |
40 | | Romain Vaslin,
Guy Gogniat,
Eduardo Wanderley Netto,
Russell Tessier,
Wayne P. Burleson:
Low latency Solution for Confidentiality and Integrity Checking in Embedded Systems with Off-Chip Memory.
ReCoSoC 2007: 146-153 |
39 | EE | Ian Kuon,
Russell Tessier,
Jonathan Rose:
FPGA Architecture: Survey and Challenges.
Foundations and Trends in Electronic Design Automation 2(2): 135-253 (2007) |
38 | EE | Russell Tessier,
Vaughn Betz,
David Neto,
Aaron Egier,
Thiagaraja Gopalsamy:
Power-Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 278-290 (2007) |
2006 |
37 | EE | Lilian Atieno,
Jonathan Allen,
Dennis Goeckel,
Russell Tessier:
An adaptive Reed-Solomon errors-and-erasures decoder.
FPGA 2006: 150-158 |
36 | EE | Russell Tessier,
Vaughn Betz,
David Neto,
Thiagaraja Gopalsamy:
Power-aware RAM mapping for FPGA embedded memory blocks.
FPGA 2006: 189-198 |
35 | EE | Premachandran R. Menon,
Weifeng Xu,
Russell Tessier:
Design-specific path delay testing in lookup-table-based FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 867-877 (2006) |
2005 |
34 | EE | Russell Tessier,
David Jasinski,
Atul Maheshwari,
Aiyappan Natarajan,
Weifeng Xu,
Wayne P. Burleson:
An energy-aware active smart card.
IEEE Trans. VLSI Syst. 13(10): 1190-1199 (2005) |
33 | EE | Russell Tessier,
Sriram Swaminathan,
Ramaswamy Ramaswamy,
Dennis Goeckel,
Wayne P. Burleson:
A reconfigurable, power-efficient adaptive Viterbi decoder.
IEEE Trans. VLSI Syst. 13(4): 484-488 (2005) |
2004 |
32 | | Russell Tessier,
Herman Schmit:
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004
ACM 2004 |
31 | EE | Jian Liang,
Russell Tessier,
Dennis Goeckel:
A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder.
FCCM 2004: 91-100 |
30 | | Atul Maheshwari,
Wayne Burleson,
Russell Tessier:
Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits.
IEEE Trans. VLSI Syst. 12(3): 299-311 (2004) |
29 | EE | Jian Liang,
Andrew Laffely,
S. Srinivasan,
Russell Tessier:
An architecture and compiler for scalable on-chip communication.
IEEE Trans. VLSI Syst. 12(7): 711-726 (2004) |
28 | EE | Prashant Jain,
Andrew Laffely,
Wayne Burleson,
Russell Tessier,
Dennis Goeckel:
Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations.
VLSI Signal Processing 36(1): 27-40 (2004) |
27 | EE | Roger Woods,
Russell Tessier:
Guest Editorial: Field Programmable Logic.
VLSI Signal Processing 36(1): 5-6 (2004) |
2003 |
26 | EE | Aiyappan Natarajan,
David Jasinski,
Wayne Burleson,
Russell Tessier:
A hybrid adiabatic content addressable memory for ultra low-power applications.
ACM Great Lakes Symposium on VLSI 2003: 72-75 |
25 | EE | Weifeng Xu,
Ramshankar Ramanarayanan,
Russell Tessier:
Adaptive Fault Recovery for Networked Reconfigurable Systems.
FCCM 2003: 143- |
24 | EE | Jian Liang,
Russell Tessier,
Oskar Mencer:
Floating Point Unit Generation and Evaluation for FPGAs.
FCCM 2003: 185-194 |
23 | | Andrew Laffely,
Jian Liang,
Russell Tessier,
Wayne Burleson:
Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores.
ICIP (3) 2003: 105-108 |
22 | EE | Srini Krishnamoorthy,
Russell Tessier:
Technology mapping algorithms for hybrid FPGAs containing lookup tables and PLAs.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 545-559 (2003) |
2002 |
21 | EE | Sriram Swaminathan,
Russell Tessier,
Dennis Goeckel,
Wayne Burleson:
A dynamically reconfigurable adaptive viterbi decoder.
FPGA 2002: 227-236 |
20 | EE | Ramaswamy Ramaswamy,
Russell Tessier:
The Integration of SystemC and Hardware-Assisted Verification.
FPL 2002: 1007-1016 |
19 | EE | Atul Maheshwari,
Wayne Burleson,
Russell Tessier:
Trading off Reliability and Power-Consumption in Ultra-low Power Systems.
ISQED 2002: 361-366 |
18 | EE | Russell Tessier:
Fast placement approaches for FPGAs.
ACM Trans. Design Autom. Electr. Syst. 7(2): 284-305 (2002) |
17 | EE | Navin Vemuri,
Priyank Kalla,
Russell Tessier:
BDD-based logic synthesis for LUT-based FPGAs.
ACM Trans. Design Autom. Electr. Syst. 7(4): 501-525 (2002) |
16 | EE | Murali Kudlugi,
Russell Tessier:
Static scheduling of multidomain circuits for fast functional verification.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1253-1268 (2002) |
15 | EE | Ian G. Harris,
Russell Tessier:
Testing and diagnosis of interconnect faults in cluster-based FPGA architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1337-1343 (2002) |
2001 |
14 | EE | Murali Kudlugi,
Charles Selvidge,
Russell Tessier:
Static Scheduling of Multiple Asynchronous Domains For Functional Verification.
DAC 2001: 647-652 |
13 | EE | Murali Kudlugi,
Charles Selvidge,
Russell Tessier:
Static Scheduling of Multi-Domain Memories For Functional Verification.
ICCAD 2001: 2-9 |
12 | | Ian G. Harris,
Premachandran R. Menon,
Russell Tessier:
BIST-based delay path testing in FPGA architectures.
ITC 2001: 932-938 |
11 | EE | Russell Tessier,
Wayne Burleson:
Reconfigurable Computing for Digital Signal Processing: A Survey.
VLSI Signal Processing 28(1-2): 7-27 (2001) |
2000 |
10 | EE | Ian G. Harris,
Russell Tessier:
Interconnect testing in cluster-based FPGA architectures.
DAC 2000: 49-54 |
9 | EE | Vijay Lakamraju,
Russell Tessier:
Tolerating operational faults in cluster-based FPGAs.
FPGA 2000: 187-194 |
8 | EE | Srini Krishnamoorthy,
Sriram Swaminathan,
Russell Tessier:
Area-Optimized Technology Mapping for Hybrid FPGAs.
FPL 2000: 181-190 |
7 | EE | Russell Tessier,
Heather Giza:
Balancing Logic Utilization and Area Efficiency in FPGAs.
FPL 2000: 535-544 |
6 | | Ian G. Harris,
Russell Tessier:
Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures.
ICCAD 2000: 472-475 |
5 | EE | Jian Liang,
Sriram Swaminathan,
Russell Tessier:
aSOC: A Scalable, Single-Chip Communications Architecture.
IEEE PACT 2000: 37-46 |
1999 |
4 | EE | Russell Tessier:
Incremental Compilation for Logic Emulation.
IEEE International Workshop on Rapid System Prototyping 1999: 236-241 |
3 | | Russell Tessier:
Frontier: A Fast Placement System for FPGAs.
VLSI 1999: 125-136 |
1997 |
2 | EE | Jonathan Babb,
Russell Tessier,
Matthew Dahl,
Silvina Hanono,
David M. Hoki,
Anant Agarwal:
Logic emulation with virtual wires.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(6): 609-626 (1997) |
1993 |
1 | EE | Steve Ward,
Karim Abdalla,
Rajeev Dujari,
Michael Fetterman,
Frank Honoré,
Ricardo Jenez,
Philippe Laffont,
Kenneth Mackenzie,
Chris Metcalf,
Milan Minsky,
John Nguyen,
John Pezaris,
Gill A. Pratt,
Russell Tessier:
The NuMesh: A Modular, Scalable Communications Substrate.
International Conference on Supercomputing 1993: 230-239 |