| 2009 |
|---|
| 93 | EE | Osman Hasan,
Naeem Abbasi,
Sofiène Tahar:
Formal Probabilistic Analysis of Stuck-at Faults in Reconfigurable Memory Arrays.
IFM 2009: 277-291 |
| 92 | EE | Osman Hasan,
Sofiène Tahar:
Performance Analysis and Functional Verification of the Stop-and-Wait Protocol in HOL.
J. Autom. Reasoning 42(1): 1-33 (2009) |
| 2008 |
|---|
| 91 | | Otmane Aït Mohamed,
César Muñoz,
Sofiène Tahar:
Theorem Proving in Higher Order Logics, 21st International Conference, TPHOLs 2008, Montreal, Canada, August 18-21, 2008. Proceedings
Springer 2008 |
| 90 | EE | Yassine Mokhtari,
Sa'ed Abed,
Otmane Aït Mohamed,
Sofiène Tahar,
Xiaoyu Song:
A New Approach for the Construction of Multiway Decision Graphs.
ICTAC 2008: 228-242 |
| 89 | EE | Osman Hasan,
Sofiène Tahar:
Performance Analysis of ARQ Protocols using a Theorem Prover.
ISPASS 2008: 85-94 |
| 88 | EE | Amjad Gawanmeh,
Sofiène Tahar,
Leila Jemni Ben Ayed:
Event-B based invariant checking of secrecy in group key protocols.
LCN 2008: 950-957 |
| 87 | EE | Aijiao Cui,
Chip-Hong Chang,
Sofiène Tahar:
IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1565-1570 (2008) |
| 86 | EE | Osman Hasan,
Sofiène Tahar:
Using Theorem Proving to Verify Expectation and Variance for Discrete Random Variables.
J. Autom. Reasoning 41(3-4): 295-323 (2008) |
| 85 | EE | Amjad Gawanmeh,
Sofiène Tahar,
Kirsten Winter:
Formal verification of ASMs using MDGs.
Journal of Systems Architecture - Embedded Systems Design 54(1-2): 15-34 (2008) |
| 2007 |
|---|
| 84 | EE | Amjad Gawanmeh,
Sofiène Tahar:
Rank Theorems for Forward Secrecy in Group Key Management Protocols.
AINA Workshops (1) 2007: 18-23 |
| 83 | EE | Osman Hasan,
Sofiène Tahar:
Formalization of Continuous Probability Distributions.
CADE 2007: 3-18 |
| 82 | EE | Ghiath Al Sammane,
Mohamed H. Zaki,
Sofiène Tahar:
A symbolic methodology for the verification of analog and mixed signal designs.
DATE 2007: 249-254 |
| 81 | EE | Tareq Hasan Khan,
Ali Habibi,
Sofiène Tahar,
Otmane Aït Mohamed:
Autometic Generation of SystemC Transactors from AsmL Specification.
FDL 2007: 104-109 |
| 80 | EE | Ghiath Al Sammane,
Mohamed H. Zaki,
Zhi Jie Dong,
Sofiène Tahar:
Towards Assertion Based Verification of Analog and Mixed Signal Designs Using PSL.
FDL 2007: 293-298 |
| 79 | EE | Mohamed H. Zaki,
Ghiath Al Sammane,
Sofiène Tahar,
Guy Bois:
Combining Symbolic Simulation and Interval Arithmetic for the Verification of AMS Designs.
FMCAD 2007: 207-215 |
| 78 | EE | Osman Hasan,
Sofiène Tahar:
Verification of Probabilistic Properties in HOL Using the Cumulative Distribution Function.
IFM 2007: 333-352 |
| 77 | | Mohamed H. Zaki,
Sofiène Tahar,
Guy Bois:
Qualitative Abstraction based Verification for Analog Circuits.
ISoLA 2007: 147-158 |
| 76 | EE | Mohamed H. Zaki,
Ghiath Al Sammane,
Sofiène Tahar:
Formal Verification of Analog and Mixed Signal Designs in Mathematica.
International Conference on Computational Science (2) 2007: 263-267 |
| 75 | EE | Osman Hasan,
Sofiène Tahar:
Verification of Expectation Properties for Discrete Random Variables in HOL.
TPHOLs 2007: 119-134 |
| 74 | EE | Haiyan Xiong,
Paul Curzon,
Sofiène Tahar,
Ann Blandford:
Providing a formal linkage between MDG and HOL.
Formal Methods in System Design 30(2): 83-116 (2007) |
| 73 | EE | Behzad Akbarpour,
Sofiène Tahar:
Error analysis of digital filters using HOL theorem proving.
J. Applied Logic 5(4): 651-666 (2007) |
| 72 | EE | Amjad Gawanmeh,
Sofiène Tahar,
Haja Moinudeen,
Ali Habibi:
A Design for Verification Approach Using an Embedding of PSL in aSML.
Journal of Circuits, Systems, and Computers 16(6): 859-881 (2007) |
| 71 | EE | Osman Hasan,
Sofiène Tahar:
Formalization of the Standard Uniform random variable.
Theor. Comput. Sci. 382(1): 71-83 (2007) |
| 2006 |
|---|
| 70 | EE | Mohamed H. Zaki,
Sofiène Tahar,
Guy Bois:
A practical approach for monitoring analog circuits.
ACM Great Lakes Symposium on VLSI 2006: 330-335 |
| 69 | EE | Amr T. Abdel-Hamid,
Sofiène Tahar,
El Mostapha Aboulhamid:
Finite State Machine IP Watermarking: A Tutorial.
AHS 2006: 457-464 |
| 68 | EE | Ali Habibi,
Sofiène Tahar,
Amer Samarah,
Donglin Li,
Otmane Aït Mohamed:
Efficient assertion based verification using TLM.
DATE 2006: 106-111 |
| 67 | EE | Jounaïdi Ben Hassen,
Sofiène Tahar:
On the numerical verification of probabilistic rewriting systems.
DATE 2006: 1223-1224 |
| 66 | EE | Ali Habibi,
Haja Moinudeen,
Sofiène Tahar:
Generating finite state machines from SystemC.
DATE Designers' Forum 2006: 76-81 |
| 65 | EE | Haja Moinudeen,
Ali Habibi,
Sofiène Tahar:
Design for Verification of the PCI-X Bus.
FMCAD 2006: 187-188 |
| 64 | EE | Abu Nasser M. Abdullah,
Behzad Akbarpour,
Sofiène Tahar:
Formal Analysis and Verification of an OFDM Modem Design using HOL.
FMCAD 2006: 189-190 |
| 63 | EE | Ali Habibi,
Haja Moinudeen,
Amer Samarah,
Sofiène Tahar:
Towards a Faster Simulation of SystemC Designs.
ISVLSI 2006: 418-419 |
| 62 | EE | Ali Habibi,
Sofiène Tahar:
Design and verification of SystemC transaction-level models.
IEEE Trans. VLSI Syst. 14(1): 57-68 (2006) |
| 61 | EE | Behzad Akbarpour,
Sofiène Tahar:
An approach for the formal verification of DSP designs using Theorem proving.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1441-1457 (2006) |
| 60 | EE | Rabeb Mizouni,
Sofiène Tahar,
Paul Curzon:
Hybrid verification integrating HOL theorem proving with MDG model checking.
Microelectronics Journal 37(11): 1200-1207 (2006) |
| 2005 |
|---|
| 59 | EE | Ali Habibi,
Sofiène Tahar:
An Approach for the Verification of SystemC Designs Using AsmL.
ATVA 2005: 69-83 |
| 58 | EE | Amjad Gawanmeh,
Ali Habibi,
Sofiène Tahar:
Embedding and Verification of PSL using AsmL.
Abstract State Machines 2005: 201-216 |
| 57 | EE | Ali Habibi,
Sofiène Tahar:
AsmL Semantics in Fixpoint.
Abstract State Machines 2005: 233-246 |
| 56 | EE | Amr T. Abdel-Hamid,
Sofiène Tahar,
El Mostapha Aboulhamid:
A Public-Key Watermarking Technique for IP Designs.
DATE 2005: 330-335 |
| 55 | EE | Ali Habibi,
Sofiène Tahar:
Design for Verification of SystemC Transaction Level Models.
DATE 2005: 560-565 |
| 54 | EE | Ali Habibi,
Sofiène Tahar:
On the Transformation of SystemC to AsmL Using Abstract Interpretation.
Electr. Notes Theor. Comput. Sci. 131: 39-49 (2005) |
| 53 | EE | Behzad Akbarpour,
Sofiène Tahar,
Abdelkader Dekdouk:
Formalization of Fixed-Point Arithmetic in HOL.
Formal Methods in System Design 27(1-2): 173-200 (2005) |
| 2004 |
|---|
| 52 | EE | Tarek Mhamdi,
Sofiène Tahar:
Providing Automated Verification in HOL Using MDGs.
ATVA 2004: 278-293 |
| 51 | EE | Fang Wang,
Sofiène Tahar,
Otmane Aït Mohamed:
First-Order LTL Model Checking Using MDGs.
ATVA 2004: 441-455 |
| 50 | EE | Ali Habibi,
Asif Iqbal Ahmed,
Otmane Aït Mohamed,
Sofiène Tahar:
On the Design and Verification Methodology of the Look-Aside Interface.
DATE 2004: 290-295 |
| 49 | EE | Ali Habibi,
Asif Iqbal Ahmed,
Otmane Aït Mohamed,
Sofiène Tahar:
On the Design and Verification Methodology of the Look-Aside Interface.
DATE 2004: 290-295 |
| 48 | EE | Amjad Gawanmeh,
Ali Habibi,
Sofiène Tahar:
Enabling SystemC Verification using Abstract State Machines.
FDL 2004: 649-661 |
| 47 | EE | Behzad Akbarpour,
Sofiène Tahar:
A Methodology for the Formal Verification of FFT Algorithms in HOL.
FMCAD 2004: 37-51 |
| 46 | | Jounaïdi Ben Hassen,
Sofiène Tahar:
Formal verification of an SoC platform protocol converter.
ISCAS (5) 2004: 313-316 |
| 45 | EE | Behzad Akbarpour,
Sofiène Tahar:
Error Analysis of Digital Filters Using Theorem Proving.
TPHOLs 2004: 1-17 |
| 44 | EE | Otmane Aït Mohamed,
Xiaoyu Song,
Eduard Cerny,
Sofiène Tahar,
Zijian Zhou:
MDG-Based State Enumeration By Retiming And Circuit Transformation.
Journal of Circuits, Systems, and Computers 13(5): 1111-1132 (2004) |
| 2003 |
|---|
| 43 | EE | Fang Wang,
Sofiène Tahar:
Language emptiness checking using MDGs.
ACM Great Lakes Symposium on VLSI 2003: 88-91 |
| 42 | EE | Amjad Gawanmeh,
Sofiène Tahar,
Kirsten Winter:
Interfacing ASM with the MDG Tool.
Abstract State Machines 2003: 278-292 |
| 41 | EE | Mohamed Layouni,
Jozef Hooman,
Sofiène Tahar:
On the Correctness of an Intrusion-Tolerant Group Communication Protocol.
CHARME 2003: 231-246 |
| 40 | EE | Behzad Akbarpour,
Sofiène Tahar:
The Application of Formal Verification to SPW Designs.
DSD 2003: 325-333 |
| 39 | EE | Behzad Akbarpour,
Sofiène Tahar:
Modeling System C Fixed-Point Arithmetic in HOL.
ICFEM 2003: 206-225 |
| 38 | EE | Hong Peng,
Sofiène Tahar,
Yassine Mokhtari:
Compositional Verification of a Switch Fabric from Nortel Networks.
ICFEM 2003: 560-578 |
| 37 | EE | Ali Habibi,
Sofiène Tahar:
A Survey oA Survey on System-On-a-Chip Designn System-On-a-Chip Design.
IWSOC 2003: 212-215 |
| 36 | EE | Amr T. Abdel-Hamid,
Sofiène Tahar,
El Mostapha Aboulhamid:
IP Watermarking Techniques: Survey and Comparison.
IWSOC 2003: 60-65 |
| 35 | EE | Amjad Gawanmeh,
Sofiène Tahar,
Kirsten Winter:
Formal Verification of ASM Designs Using the MDG Tool.
SEFM 2003: 210-219 |
| 34 | EE | Hong Peng,
Sofiène Tahar,
Ferhat Khendek:
Comparison of SPIN and VIS for protocol verification.
STTT 4(2): 234-245 (2003) |
| 33 | EE | Skander Kort,
Sofiène Tahar,
Paul Curzon:
Hierarchical formal verification using a hybrid tool.
STTT 4(3): 313-322 (2003) |
| 2002 |
|---|
| 32 | | Victor Carreño,
César Muñoz,
Sofiène Tahar:
Theorem Proving in Higher Order Logics, 15th International Conference, TPHOLs 2002, Hampton, VA, USA, August 20-23, 2002, Proceedings
Springer 2002 |
| 31 | EE | Ali Habibi,
Sofiène Tahar,
Adel Ghazel:
Formal Verification of a DSP Chip Using an Iterative Approach.
DSD 2002: 12-19 |
| 30 | EE | Hong Peng,
Yassine Mokhtari,
Sofiène Tahar:
Environment Synthesis for Compositional Model Checking.
ICCD 2002: 70- |
| 29 | EE | M. Hasan Zobair,
Sofiène Tahar:
Formal Verification of a SONET Telecom System Block.
ICFEM 2002: 447-458 |
| 28 | EE | Amr T. Abdel-Hamid,
Sofiène Tahar,
John Harrison:
Enabling Hardware Verification through Design Changes.
ICFEM 2002: 459-470 |
| 27 | EE | Behzad Akbarpour,
Abdelkader Dekdouk,
Sofiène Tahar:
Formalization of Cadence SPW Fixed-Point Arithmetic in HOL.
IFM 2002: 185-204 |
| 26 | EE | Haiyan Xiong,
Paul Curzon,
Sofiène Tahar,
Ann Blandford:
Formally Linking MDG and HOL Based on a Verified MDG System.
IFM 2002: 205-224 |
| 2001 |
|---|
| 25 | EE | Leila Barakatain,
Sofiène Tahar,
Jean Lamarche,
Jean-Marc Gendreau:
Practical approaches to the verification of a telecom megacell using FormalCheck.
ACM Great Lakes Symposium on VLSI 2001: 1-6 |
| 24 | EE | Iskander Kort,
Sofiène Tahar,
Paul Curzon:
Hierarchical Verification Using an MDG-HOL Hybrid Tool.
CHARME 2001: 244-258 |
| 2000 |
|---|
| 23 | EE | V. K. Pisini,
Sofiène Tahar,
Paul Curzon,
Otmane Aït Mohamed,
Xiaoyu Song:
Formal hardware verification by integrating HOL and MDG.
ACM Great Lakes Symposium on VLSI 2000: 23-28 |
| 22 | | Jian F. Weng,
Guo Q. Xue,
Tho Le-Ngoc,
Sofiène Tahar:
Analysis of Multilevel-Quantized Soft-Limiting Detector for an FH-SSMA System.
ICC (3) 2000: 1380-1384 |
| 21 | EE | Hong Peng,
Sofiène Tahar,
Ferhat Khendek:
SPIN vs. VIS: A Case Study on the Formal Verification of the ATMR Protocol.
ICFEM 2000: 79-88 |
| 20 | EE | Mostafa Azizi,
El Mostapha Aboulhamid,
Sofiène Tahar:
Sequential and Distributed Simulations Using Java Threads.
PARELEC 2000: 237-243 |
| 1999 |
|---|
| 19 | EE | Subhashini Balakrishnan,
Sofiène Tahar:
A Hierarchical Approach to the Formal Verification of Embedded Systems Using MDGs.
Great Lakes Symposium on VLSI 1999: 284-287 |
| 18 | | Mostafa Azizi,
El Mostapha Aboulhamid,
Sofiène Tahar:
Multithreading-based Coverification Technique of HW/SW Systems.
PDPTA 1999: 1999-2005 |
| 17 | EE | Haiyan Xiong,
Paul Curzon,
Sofiène Tahar:
Importing MDG Verification Results into HOL.
TPHOLs 1999: 293-310 |
| 16 | EE | Sofiène Tahar,
Xiaoyu Song,
Eduard Cerny,
Zijian Zhou,
Michel Langevin,
Otmane Aït Mohamed:
Modeling and formal verification of the Fairisle ATM switch fabricusing MDGs.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(7): 956-972 (1999) |
| 15 | | Sofiène Tahar,
Paul Curzon:
Comparing HOL and MDG: a Case Study on the Verification of an ATM Switch Fabric.
Nord. J. Comput. 6(4): 372-402 (1999) |
| 1998 |
|---|
| 14 | EE | Sofiène Tahar,
Paul Curzon,
Jianping Lu:
Three Approaches to Hardware Verification: HOL, MDG and VIS Compared.
FMCAD 1998: 433-450 |
| 13 | EE | Jianping Lu,
Sofiène Tahar:
Practical Approaches to the Automatic Verification of an ATM Switch Fabric Using VIS.
Great Lakes Symposium on VLSI 1998: 368- |
| 12 | | Sofiène Tahar,
Ramayya Kumar:
A Practical Methodology for the Formal Verification of RISC Processors.
Formal Methods in System Design 13(2): 159-225 (1998) |
| 1997 |
|---|
| 11 | | Eduard Cerny,
Francisco Corella,
Michel Langevin,
Xiaoyu Song,
Sofiène Tahar,
Zijian Zhou:
Verification with Abstract State Machines Using MDGs.
Formal Hardware Verification 1997: 79-113 |
| 1996 |
|---|
| 10 | | K. D. Anon,
N. Boulerice,
Eduard Cerny,
Francisco Corella,
Michel Langevin,
Xiaoyu Song,
Sofiène Tahar,
Ying Xu,
Zijian Zhou:
MDG Tools for the Verification of RTL Designs.
CAV 1996: 433-436 |
| 9 | | Zijian Zhou,
Xiaoyu Song,
Sofiène Tahar,
Eduard Cerny,
Francisco Corella,
Michel Langevin:
Formal Verification of the Island Tunnel Controller Using Multiway Decision Graphs.
FMCAD 1996: 233-247 |
| 8 | EE | Sofiène Tahar,
Zijian Zhou,
Xiaoyu Song,
Eduard Cerny,
Michel Langevin:
Formal Verification of an ATM Switch Fabric using Multiway Decision Graphs.
Great Lakes Symposium on VLSI 1996: 106-111 |
| 7 | EE | Michel Langevin,
Sofiène Tahar,
Zijian Zhou,
Xiaoyu Song,
Eduard Cerny:
Behavioral Verification of an ATM Switch Fabric using Implicit Abstract State Enumeration.
ICCD 1996: 20-26 |
| 6 | | Sofiène Tahar,
Paul Curzon:
A Comparison of MDG and HOL for Hardware Verification.
TPHOLs 1996: 415-430 |
| 1995 |
|---|
| 5 | | Sofiène Tahar,
Ramayya Kumar:
Formal Specification and Verification Techniques for RISC Pipeline Conflicts.
Comput. J. 38(2): 111-120 (1995) |
| 1994 |
|---|
| 4 | EE | Ramayya Kumar,
Sofiène Tahar:
Formal verification of pipeline conflicts in RISC processors.
EURO-DAC 1994: 284-289 |
| 3 | | Sofiène Tahar,
Ramayya Kumar:
Implementational Issues for Verifying RISC-Pipeline Conflicts in HOL.
TPHOLs 1994: 424-439 |
| 1993 |
|---|
| 2 | | Sofiène Tahar,
Ramayya Kumar:
Implementing a Methodology for Formally Verifying RISC Processors in HOL.
HUG 1993: 281-294 |
| 1 | | Sofiène Tahar,
Ramayya Kumar:
Towards a Methodology for the Formal Hierarchical Verification.
ICCD 1993: 58-62 |
