Cliff C. N. Sze

Chin Ngai Sze, Cliff N. Sze

2008
19	EE	Gi-Joon Nam, Cliff C. N. Sze, Mehmet Can Yildiz: The ISPD global routing benchmark suite. ISPD 2008: 156-159
2007
18	EE	Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz: The nuts and bolts of physical synthesis. SLIP 2007: 89-94
2006
17	EE	Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze: Fast algorithms for slew constrained minimum cost buffering. DAC 2006: 308-313
16	EE	Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang: Timing-driven Steiner trees are (practically) free. DAC 2006: 389-392
15	EE	Ganesh Venkataraman, Jiang Hu, Frank Liu, Cliff C. N. Sze: Integrated placement and skew optimization for rotary clocking. DATE 2006: 756-761
14	EE	Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze: Accurate estimation of global buffer delay within a floorplan. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1140-1145 (2006)
2005
13	EE	Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi: Making fast buffer insertion even faster via approximation techniques. ASP-DAC 2005: 13-18
12	EE	Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu: Register placement for low power clock network. ASP-DAC 2005: 588-593
11	EE	Ganesh Venkataraman, Cliff C. N. Sze, Jiang Hu: Skew scheduling and clock routing for improved tolerance to process variations. ASP-DAC 2005: 594-599
10	EE	Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu: Navigating registers in placement for clock network minimization. DAC 2005: 176-181
9	EE	Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi: Path based buffer insertion. DAC 2005: 509-514
2004
8	EE	Cliff C. N. Sze, Jiang Hu, Charles J. Alpert: A place and route aware buffered Steiner tree construction. ASP-DAC 2004: 355-360
7	EE	Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze: Accurate estimation of global buffer delay within a floorplan. ICCAD 2004: 706-711
6	EE	Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze: Porosity-aware buffered Steiner tree construction. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 517-526 (2004)
5	EE	Cliff C. N. Sze, Ting-Chi Wang, Li-C. Wang: Multilevel circuit clustering for delay minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1073-1085 (2004)
2003
4	EE	Cliff C. N. Sze, Ting-Chi Wang: Optimal circuit clustering for delay minimization under a more general delay model. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 646-651 (2003)
2002
3	EE	Cliff C. N. Sze, Ting-Chi Wang: Optimal circuit clustering with variable interconnect delay. ISCAS (4) 2002: 707-710
2		Cliff C. N. Sze, Ting-Chi Wang: Multi-Level Circuit Clustering for Delay Minimization. IWLS 2002: 227-232
2001
1	EE	Chin Ngai Sze, Yu-Liang Wu: Improved alternative wiring scheme applying dominator relationship. ASP-DAC 2001: 473-478

Coauthor Index

1	Charles J. Alpert	[6] [7] [8] [9] [13] [14] [16] [17] [18]
2	Yici Cai	[10] [12]
3	Gopal Gandham	[6]
4	Xianlong Hong	[10] [12]
5	Milos Hrkic	[6]
6	Jiang Hu	[6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [17]
7	Shiyan Hu	[17]
8	Liang Huang	[10] [12]
9	Andrew B. Kahng	[16]
10	Shrirang K. Karandikar	[17] [18]
11	Zhuo Li	[13] [17] [18]
12	Frank Liu	[15]
13	Yongqiang Lu	[10] [12]
14	Gi-Joon Nam	[18] [19]
15	Stephen T. Quay	[6] [18]
16	Haoxing Ren	[18]
17	Sachin S. Sapatnekar	[7] [14]
18	Weiping Shi	[9] [13] [17]
19	Ganesh Venkataraman	[11] [15]
20	Paul G. Villarrubia (Paul Villarrubia)	[18]
21	Li-C. Wang	[5]
22	Qinke Wang	[16]
23	Ting-Chi Wang	[2] [3] [4] [5]
24	Yu-Liang Wu (David Yu-Liang Wu)	[1]
25	Mehmet Can Yildiz	[18] [19]
26	Qiang Zhou	[10] [12]

Colors in the list of coauthors