2008 |
28 | EE | Seongmoon Wang,
Kedarnath J. Balakrishnan,
Wenlong Wei:
X-Block: An Efficient LFSR Reseeding-Based Method to Block Unknowns for Temporal Compactors.
IEEE Trans. Computers 57(7): 978-989 (2008) |
27 | EE | Seongmoon Wang,
Wenlong Wei:
An Efficient Unknown BlockingScheme for Low Control Data Volume and High Observability.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 2039-2052 (2008) |
2007 |
26 | EE | Seongmoon Wang,
Wenlong Wei:
A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture.
ASP-DAC 2007: 810-816 |
25 | EE | Zhanglei Wang,
Krishnendu Chakrabarty,
Seongmoon Wang:
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling.
DATE 2007: 201-206 |
24 | EE | Seongmoon Wang,
Wenlong Wei,
Srimat T. Chakradhar:
Unknown blocking scheme for low control data volume and high observability.
DATE 2007: 33-38 |
23 | EE | Mango Chia-Tso Chao,
Kwang-Ting Cheng,
Seongmoon Wang,
Srimat T. Chakradhar,
Wenlong Wei:
A hybrid scheme for compacting test responses with unknown values.
ICCAD 2007: 513-519 |
22 | EE | Rajamani Sethuram,
Seongmoon Wang,
Srimat T. Chakradhar,
Michael L. Bushnell:
Zero Cost Test Point Insertion Technique for Structured ASICs.
VLSI Design 2007: 357-363 |
21 | EE | Seongmoon Wang:
A BIST TPG for Low Power Dissipation and High Fault Coverage.
IEEE Trans. VLSI Syst. 15(7): 777-789 (2007) |
2006 |
20 | EE | Mango Chia-Tso Chao,
Kwang-Ting Cheng,
Seongmoon Wang,
Srimat T. Chakradhar,
Wenlong Wei:
Unknown-tolerance analysis and test-quality control for test response compaction using space compactors.
DAC 2006: 1083-1088 |
19 | EE | Seongmoon Wang,
Kedarnath J. Balakrishnan,
Srimat T. Chakradhar:
Efficient unknown blocking using LFSR reseeding.
DATE 2006: 1051-1052 |
18 | EE | Mango Chia-Tso Chao,
Seongmoon Wang,
Srimat T. Chakradhar,
Wenlong Wei,
Kwang-Ting Cheng:
Coverage loss by using space compactors in presence of unknown values.
DATE 2006: 1053-1054 |
17 | EE | Kedarnath J. Balakrishnan,
Seongmoon Wang,
Srimat T. Chakradhar:
PIDISC: Pattern Independent Design Independent Seed Compression Technique.
VLSI Design 2006: 811-817 |
16 | EE | Seongmoon Wang,
Srimat T. Chakradhar:
A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1555-1564 (2006) |
15 | EE | Seongmoon Wang,
Sandeep K. Gupta:
LT-RTPG: a new test-per-scan BIST TPG for low switching activity.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1565-1574 (2006) |
2005 |
14 | | Mango Chia-Tso Chao,
Seongmoon Wang,
Srimat T. Chakradhar,
Kwang-Ting Cheng:
Response shaper: a novel technique to enhance unknown tolerance for output response compaction.
ICCAD 2005: 80-87 |
13 | EE | Mango Chia-Tso Chao,
Seongmoon Wang,
Srimat T. Chakradhar,
Kwang-Ting Cheng:
ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values.
ICCD 2005: 147-152 |
12 | EE | Wei Li,
Seongmoon Wang,
Srimat T. Chakradhar,
Sudhakar M. Reddy:
Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage.
VLSI Design 2005: 471-478 |
2004 |
11 | EE | Seongmoon Wang,
Srimat T. Chakradhar,
Kedarnath J. Balakrishnan:
Re-configurable embedded core test protocol.
ASP-DAC 2004: 234-237 |
10 | EE | Seongmoon Wang,
Xiao Liu,
Srimat T. Chakradhar:
Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets.
DATE 2004: 1296-1301 |
2003 |
9 | EE | Seongmoon Wang,
Srimat T. Chakradhar:
A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs.
ITC 2003: 574-583 |
2002 |
8 | EE | Seongmoon Wang:
Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST.
ITC 2002: 834-843 |
7 | EE | Seongmoon Wang,
Sandeep K. Gupta:
DS-LFSR: a BIST TPG for low switching activity.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 842-851 (2002) |
6 | EE | Seongmoon Wang,
Sandeep K. Gupta:
An automatic test pattern generator for minimizing switching activity during scan testing activity.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(8): 954-968 (2002) |
1999 |
5 | | Seongmoon Wang,
Sandeep K. Gupta:
LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation.
ITC 1999: 85-94 |
1998 |
4 | | Seongmoon Wang,
Sandeep K. Gupta:
ATPG for Heat Dissipation Minimization During Test Application.
IEEE Trans. Computers 47(2): 256-262 (1998) |
1997 |
3 | EE | Seongmoon Wang,
Sandeep K. Gupta:
ATPG for Heat Dissipation Minimization During Scan Testing.
DAC 1997: 614-619 |
2 | | Seongmoon Wang,
Sandeep K. Gupta:
DS-LFSR: A New BIST TPG for Low Heat Dissipation.
ITC 1997: 848-857 |
1994 |
1 | | Seongmoon Wang,
Sandeep K. Gupta:
ATPG for Heat Dissipation Minimization During Test Application.
ITC 1994: 250-258 |