| 2006 |
|---|
| 5 | EE | Chandramouli Visweswariah,
K. Ravindran,
K. Kalafala,
Steven G. Walker,
S. Narayan,
Daniel K. Beece,
J. Piaget,
N. Venkateswaran,
Jeffrey G. Hemmett:
First-Order Incremental Block-Based Statistical Timing Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2170-2180 (2006) |
| 2004 |
|---|
| 4 | EE | Chandramouli Visweswariah,
K. Ravindran,
K. Kalafala,
Steven G. Walker,
S. Narayan:
First-order incremental block-based statistical timing analysis.
DAC 2004: 331-336 |
| 2001 |
|---|
| 3 | EE | Phillip Restle,
Albert E. Ruehli,
Steven G. Walker:
Multi-GHz interconnect effects in microprocessors.
ISPD 2001: 93-97 |
| 2 | EE | Phillip Restle,
Albert E. Ruehli,
Steven G. Walker,
George Papadopoulos:
Full-wave PEEC time-domain method for the modeling of on-chipinterconnects.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(7): 877-886 (2001) |
| 1999 |
|---|
| 1 | EE | Phillip Restle,
Albert E. Ruehli,
Steven G. Walker:
Dealing with Inductance in High-Speed Chip Design.
DAC 1999: 904-909 |
