2008 |
14 | EE | Aditya Bansal,
Rama N. Singh,
Saibal Mukhopadhyay,
Geng Han,
Fook-Luen Heng,
Ching-Te Chuang:
Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield.
ICCD 2008: 457-462 |
13 | EE | Aditya Bansal,
Jae-Joon Kim,
Keunwoo Kim,
Saibal Mukhopadhyay,
Ching-Te Chuang,
Kaushik Roy:
Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies.
VLSI Design 2008: 125-130 |
12 | EE | Jing Li,
Aditya Bansal,
Swaroop Ghosh,
Kaushik Roy:
An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs.
JETC 4(3): (2008) |
2007 |
11 | EE | Jing Li,
Kunhyuk Kang,
Aditya Bansal,
Kaushik Roy:
High Performance and Low Power Electronics on Flexible Substrate.
DAC 2007: 274-275 |
10 | EE | Jung Hwan Choi,
Aditya Bansal,
Mesut Meterelliyoz,
Jayathi Murthy,
Kaushik Roy:
Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2059-2068 (2007) |
2006 |
9 | EE | Aditya Bansal,
Mesut Meterelliyoz,
Siddharth Singh,
Jung Hwan Choi,
Jayathi Murthy,
Kaushik Roy:
Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology.
ASP-DAC 2006: 237-242 |
8 | EE | Mark M. Budnik,
Arijit Raychowdhury,
Aditya Bansal,
Kaushik Roy:
A high density, carbon nanotube capacitor for decoupling applications.
DAC 2006: 935-938 |
7 | EE | Qikai Chen,
Saibal Mukhopadhyay,
Aditya Bansal,
Kaushik Roy:
Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design.
DATE 2006: 983-988 |
6 | EE | Jung Hwan Choi,
Aditya Bansal,
Mesut Meterelliyoz,
Jayathi Murthy,
Kaushik Roy:
Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits.
ICCAD 2006: 583-586 |
5 | EE | Kaushik Roy,
Hamid Mahmoodi-Meimand,
Saibal Mukhopadhyay,
Hari Ananthan,
Aditya Bansal,
Tamer Cakici:
Double-Gate SOI Devices for Low-Power and High-Performance Applications.
VLSI Design 2006: 445-452 |
4 | EE | Aditya Bansal,
Bipul Chandra Paul,
Kaushik Roy:
An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2765-2774 (2006) |
2005 |
3 | | Kaushik Roy,
Hamid Mahmoodi-Meimand,
Saibal Mukhopadhyay,
Hari Ananthan,
Aditya Bansal,
Tamer Cakici:
Double-gate SOI devices for low-power and high-performance applications.
ICCAD 2005: 217-224 |
2 | EE | Aditya Bansal,
Kaushik Roy:
Asymmetric halo CMOSFET to reduce static power dissipation with improved performance.
ISCAS (1) 2005: 1-4 |
2004 |
1 | EE | Hari Ananthan,
Aditya Bansal,
Kaushik Roy:
FinFET SRAM - Device and Circuit Design Considerations.
ISQED 2004: 511-516 |