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Aditya Bansal

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2008
14EEAditya Bansal, Rama N. Singh, Saibal Mukhopadhyay, Geng Han, Fook-Luen Heng, Ching-Te Chuang: Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield. ICCD 2008: 457-462
13EEAditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy: Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. VLSI Design 2008: 125-130
12EEJing Li, Aditya Bansal, Swaroop Ghosh, Kaushik Roy: An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs. JETC 4(3): (2008)
2007
11EEJing Li, Kunhyuk Kang, Aditya Bansal, Kaushik Roy: High Performance and Low Power Electronics on Flexible Substrate. DAC 2007: 274-275
10EEJung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy: Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2059-2068 (2007)
2006
9EEAditya Bansal, Mesut Meterelliyoz, Siddharth Singh, Jung Hwan Choi, Jayathi Murthy, Kaushik Roy: Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology. ASP-DAC 2006: 237-242
8EEMark M. Budnik, Arijit Raychowdhury, Aditya Bansal, Kaushik Roy: A high density, carbon nanotube capacitor for decoupling applications. DAC 2006: 935-938
7EEQikai Chen, Saibal Mukhopadhyay, Aditya Bansal, Kaushik Roy: Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design. DATE 2006: 983-988
6EEJung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy: Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits. ICCAD 2006: 583-586
5EEKaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici: Double-Gate SOI Devices for Low-Power and High-Performance Applications. VLSI Design 2006: 445-452
4EEAditya Bansal, Bipul Chandra Paul, Kaushik Roy: An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2765-2774 (2006)
2005
3 Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici: Double-gate SOI devices for low-power and high-performance applications. ICCAD 2005: 217-224
2EEAditya Bansal, Kaushik Roy: Asymmetric halo CMOSFET to reduce static power dissipation with improved performance. ISCAS (1) 2005: 1-4
2004
1EEHari Ananthan, Aditya Bansal, Kaushik Roy: FinFET SRAM - Device and Circuit Design Considerations. ISQED 2004: 511-516

Coauthor Index

1Hari Ananthan [1] [3] [5]
2Mark M. Budnik [8]
3Tamer Cakici [3] [5]
4Qikai Chen [7]
5Jung Hwan Choi [6] [9] [10]
6Ching-Te Chuang [13] [14]
7Swaroop Ghosh [12]
8Geng Han [14]
9Fook-Luen Heng [14]
10Kunhyuk Kang [11]
11Jae-Joon Kim [13]
12Keunwoo Kim [13]
13Jing Li [11] [12]
14Hamid Mahmoodi (Hamid Mahmoodi-Meimand) [3] [5]
15Mesut Meterelliyoz [6] [9] [10]
16Saibal Mukhopadhyay [3] [5] [7] [13] [14]
17Jayathi Murthy [6] [9] [10]
18Bipul Chandra Paul (Bipul C. Paul) [4]
19Arijit Raychowdhury [8]
20Kaushik Roy [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
21Rama N. Singh [14]
22Siddharth Singh [9]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)