2008 |
8 | EE | Jaskirat Singh,
Sachin S. Sapatnekar:
A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and Gaussian Parameter Variations.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 160-173 (2008) |
7 | EE | Jaskirat Singh,
Zhi-Quan Luo,
Sachin S. Sapatnekar:
A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 295-308 (2008) |
2006 |
6 | EE | Jaskirat Singh,
Sachin S. Sapatnekar:
Statistical timing analysis with correlated non-gaussian parameters using independent component analysis.
DAC 2006: 155-160 |
5 | EE | Jaskirat Singh,
Sachin S. Sapatnekar:
Partition-Based Algorithm for Power Grid Design Using Locality.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 664-677 (2006) |
2005 |
4 | EE | Jaskirat Singh,
Vidyasagar Nookala,
Zhi-Quan Luo,
Sachin S. Sapatnekar:
Robust gate sizing by geometric programming.
DAC 2005: 315-320 |
3 | EE | Jaskirat Singh,
Sachin S. Sapatnekar:
A fast algorithm for power grid design.
ISPD 2005: 70-77 |
2 | EE | Jaskirat Singh,
Sachin S. Sapatnekar:
Congestion-aware topology optimization of structured power/ground networks.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 683-695 (2005) |
2004 |
1 | EE | Jaskirat Singh,
Sachin S. Sapatnekar:
Topology optimization of structured power/ground networks.
ISPD 2004: 116-123 |