| 2006 |
|---|
| 8 | EE | Mahilchi Milir Vaseekar Kumar,
Spyros Tragoudas,
Sreejit Chakravarty,
Rathish Jayabharathi:
Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2954-2964 (2006) |
| 2005 |
|---|
| 7 | EE | Mahilchi Milir Vaseekar Kumar,
Spyros Tragoudas,
Sreejit Chakravarty,
Rathish Jayabharathi:
Implicit and Exact Path Delay Fault Grading in Sequential Circuits.
DATE 2005: 990-995 |
| 2001 |
|---|
| 6 | EE | Kee Sup Kim,
Rathish Jayabharathi,
Craig Carstens:
SpeedGrade: An RTL Path Delay Fault Simulator.
Asian Test Symposium 2001: 239-243 |
| 5 | | Kee Sup Kim,
Rathish Jayabharathi,
Craig Carstens,
Praveen Vishakantaiah,
Derek Feltham,
Adrian Carbine:
DPDAT: data path direct access testing.
ITC 2001: 188-195 |
| 1999 |
|---|
| 4 | | Rathish Jayabharathi,
Manuel A. d'Abreu,
Jacob A. Abraham:
FzCRITIC - A Functional Timing Verifier Using a Novel Fuzzy Delay Model.
VLSI Design 1999: 232-235 |
| 1997 |
|---|
| 3 | EE | Rathish Jayabharathi,
Kyung Tek Lee,
Jacob A. Abraham:
A Novel Solution for Chip-Level Functional Timing Verification.
VTS 1997: 137-142 |
| 1996 |
|---|
| 2 | EE | Abhijit Chatterjee,
Rathish Jayabharathi,
Pankaj Pant,
Jacob A. Abraham:
Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages.
VTS 1996: 354-361 |
| 1993 |
|---|
| 1 | | Rathish Jayabharathi,
Thomas Thomas,
Earl E. Swartzlander Jr.:
A Comparative Evaluation of Adders Based on Performance and Testability.
ICCD 1993: 314-317 |
