2008 | ||
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18 | EE | Desta Tadesse, R. Iris Bahar, Joel Grodstein: Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation. VTS 2008: 339-344 |
2007 | ||
17 | EE | Desta Tadesse, D. Sheffield, E. Lenge, R. Iris Bahar, Joel Grodstein: Accurate timing analysis using SAT and pattern-dependent delay models. DATE 2007: 1018-1023 |
2006 | ||
16 | EE | Hui-Yuan Song, Kundan Nepal, R. Iris Bahar, Joel Grodstein: Timing analysis for full-custom circuits using symbolic DC formulations. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1815-1830 (2006) |
2005 | ||
15 | EE | R. Iris Bahar, Hui-Yuan Song, Kundan Nepal, Joel Grodstein: Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 502-515 (2005) |
2004 | ||
14 | EE | Kundan Nepal, Hui-Yuan Song, R. Iris Bahar, Joel Grodstein: RESTA: a robust and extendable symbolic timing analysis tool. ACM Great Lakes Symposium on VLSI 2004: 407-412 |
2003 | ||
13 | EE | Joel Grodstein, Dilip K. Bhavsar, Vijay Bettada, Richard A. Davies: Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor. ICCD 2003: 180-186 |
12 | EE | Hui-Yuan Song, S. Bohidar, R. Iris Bahar, Joel Grodstein: Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current. ICCD 2003: 70-75 |
2002 | ||
11 | EE | Joel Grodstein, Rachid Rayess, Tad Truex, Linda Shattuck, Sue Lowell, Dan Bailey, David Bertucci, Gabriel P. Bischoff, Daniel E. Dever, Mike Gowan, Roy Lane, Brian Lilly, Krishna Nagalla, Rahul Shah, Emily Shriver, Shi-Huang Yin, Shannon V. Morton: Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU. ACM Great Lakes Symposium on VLSI 2002: 1-6 |
10 | Hui-Yuan Song, R. Iris Bahar, Joel Grodstein: Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations. IWLS 2002: 203-208 | |
1997 | ||
9 | EE | Eric Lehman, Yosinatori Watanabe, Joel Grodstein, Heather Harkness: Logic decomposition during technology mapping. IEEE Trans. on CAD of Integrated Circuits and Systems 16(8): 813-834 (1997) |
1995 | ||
8 | EE | Eric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness: Logic decomposition during technology mapping. ICCAD 1995: 264-271 |
7 | EE | Joel Grodstein, Eric Lehman, Heather Harkness, Bill Grundmann, Yosinatori Watanabe: A delay model for logic synthesis of continuously-sized networks. ICCAD 1995: 458-462 |
1994 | ||
6 | EE | Joel Grodstein, Eric Lehman, Heather Harkness, Hervé J. Touati, Bill Grundmann: Optimal latch mapping and retiming within a tree. ICCAD 1994: 242-245 |
1993 | ||
5 | EE | K. Kodandapani, Joel Grodstein, Antun Domic, Hervé J. Touati: A simple algorithm for fanout optimization using high-performance buffer libraries. ICCAD 1993: 466-471 |
1991 | ||
4 | EE | Jengwei Pan, Larry L. Biro, Joel Grodstein, William J. Grundmann, Yao-Tsung Yen: Timing Verification on a 1.2M-Device Full-Custom CMOS Design. DAC 1991: 551-554 |
3 | Joel Grodstein, Nick Rethman, Rahul Razdan, Gabriel P. Bischoff: Automatic Detection of MOS Synchronizers for Timing Verification. ICCAD 1991: 304-307 | |
1990 | ||
2 | Joel Grodstein, Jengwei Pan, William J. Grundmann, Bruce Gieseke, Yao-Tsung Yen: Constraint Identification for Timing Verification. ICCAD 1990: 16-19 | |
1 | Joel Grodstein, Jim Montanaro, Susanne Marino: Race Detection for Two-Phase Systems. ICCAD 1990: 20-23 |