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Alan Mishchenko

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2009
51EEAlan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang: Scalable don't-care-based logic optimization and resynthesis. FPGA 2009: 151-160
50EEStephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton: SmartOpt: an industrial strength framework for logic synthesis. FPGA 2009: 237-240
2008
49EEAaron P. Hurst, Alan Mishchenko, Robert K. Brayton: Scalable min-register retiming under timing and initializability constraints. DAC 2008: 534-539
48EEMichael L. Case, Victor N. Kravets, Alan Mishchenko, Robert K. Brayton: Merging nodes under sequential observability. DAC 2008: 540-545
47EEStephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko: WireMap: FPGA technology mapping for improved routability. FPGA 2008: 47-55
46EEAlan Mishchenko, Michael L. Case, Robert K. Brayton, Stephen Jang: Scalable and scalably-verifiable sequential synthesis. ICCAD 2008: 234-241
45EEAlan Mishchenko, Robert K. Brayton, Satrajit Chatterjee: Boolean factoring and decomposition of logic networks. ICCAD 2008: 38-44
2007
44EESatrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Andreas Kuehlmann: On Resolution Proofs for Combinational Equivalence. DAC 2007: 600-605
43EEMichael L. Case, Alan Mishchenko, Robert K. Brayton: Automated Extraction of Inductive Invariants to Aid Model Checking. FMCAD 2007: 165-172
42EEAaron P. Hurst, Alan Mishchenko, Robert K. Brayton: Fast Minimum-Register Retiming via Binary Maximum-Flow. FMCAD 2007: 181-187
41EEChih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang Huang, Alan Mishchenko: Scalable exploration of functional dependency by interpolation and incremental SAT solving. ICCAD 2007: 227-233
40EEAlan Mishchenko, Sungmin Cho, Satrajit Chatterjee, Robert K. Brayton: Combinational and sequential mapping with priority cuts. ICCAD 2007: 354-361
39EENiklas Eén, Alan Mishchenko, Niklas Sörensson: Applying Logic Synthesis for Speeding Up SAT. SAT 2007: 272-286
38EEAlan Mishchenko, Robert K. Brayton: SAT-Based Complete Don't-Care Computation for Network Optimization CoRR abs/0710.4695: (2007)
37EEAlan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko: Efficient Solution of Language Equations Using Partitioned Representations CoRR abs/0710.4743: (2007)
36EEAlan Mishchenko, Satrajit Chatterjee, Robert K. Brayton: Improvements to Technology Mapping for LUT-Based FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 26(2): 240-253 (2007)
2006
35EEJin S. Zhang, Alan Mishchenko, Robert K. Brayton, Malgorzata Chrzanowska-Jeske: Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability. DAC 2006: 510-515
34EEAlan Mishchenko, Satrajit Chatterjee, Robert K. Brayton: DAG-aware AIG rewriting a fresh look at combinational logic synthesis. DAC 2006: 532-535
33EEAlan Mishchenko, Satrajit Chatterjee, Robert K. Brayton: Improvements to technology mapping for LUT-based FPGAs. FPGA 2006: 41-49
32EESatrajit Chatterjee, Alan Mishchenko, Robert K. Brayton: Factor cuts. ICCAD 2006: 143-150
31EEAlan Mishchenko, Satrajit Chatterjee, Robert K. Brayton, Niklas Eén: Improvements to combinational equivalence checking. ICCAD 2006: 836-843
30EESatrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam: Reducing Structural Bias in Technology Mapping. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2894-2903 (2006)
29EEAlan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske: Using simulation and satisfiability to compute flexibilities in Boolean networks. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 743-755 (2006)
28EEJin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch: Linear cofactor relationships in Boolean functions. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1011-1023 (2006)
27EEAlan Mishchenko, Robert K. Brayton: A theory of nondeterministic networks. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 977-999 (2006)
2005
26EEJin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch: Detecting support-reducing bound sets using two-cofactor symmetries. ASP-DAC 2005: 266-271
25EEAlan Mishchenko, Robert K. Brayton: SAT-Based Complete Don't-Care Computation for Network Optimization. DATE 2005: 412-417
24EEAlan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko: Efficient Solution of Language Equations Using Partitioned Representations. DATE 2005: 418-423
23 Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam: Reducing structural bias in technology mapping. ICCAD 2005: 519-526
22EEMalgorzata Chrzanowska-Jeske, Alan Mishchenko: Synthesis for regularity using decision diagrams [logic IC synthesis and layout]. ISCAS (5) 2005: 4721-4724
2004
21EEJie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton: On breakable cyclic definitions. ICCAD 2004: 411-418
2003
20EEAlan Mishchenko, Xinning Wang, Timothy Kam: A new enhanced constructive decomposition and mapping algorithm. DAC 2003: 143-148
19EEAlan Mishchenko, Tsutomu Sasao: Large-scale SOP minimization using decomposition and functional properties. DAC 2003: 149-154
18EEJie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton: Reducing Multi-Valued Algebraic Operations to Binary. DATE 2003: 10752-10757
17EEAlan Mishchenko, Robert K. Brayton: A Theory of Non-Deterministic Networks. ICCAD 2003: 709-717
16EEXiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Andrew A. Kennings, Alan J. Coppola: Board-level multiterminal net assignment for the partial cross-bar architecture. IEEE Trans. VLSI Syst. 11(3): 511-514 (2003)
15EEAlan Mishchenko: Fast computation of symmetries in Boolean functions. IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1588-1593 (2003)
2002
14EEXiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Alan J. Coppola, Andrew A. Kennings: Board-level multiterminal net assignment. ACM Great Lakes Symposium on VLSI 2002: 130-135
13EEAlan Mishchenko, Robert K. Brayton: Simplification of non-deterministic multi-valued networks. ICCAD 2002: 557-562
12EESubarnarekha Sinha, Alan Mishchenko, Robert K. Brayton: Topologically constrained logic synthesis. ICCAD 2002: 679-686
11EERobert K. Brayton, M. Gao, Jie-Hong Roland Jiang, Yunjian Jiang, Yinghua Li, Alan Mishchenko, Subarnarekha Sinha, Tiziano Villa: Optimization of Multi-Valued Multi-Level Networks. ISMVL 2002: 168-
10 Alan Mishchenko, Tsutomu Sasao: Encoding of Boolean Functions and its Application to LUT Cascade Synthesis. IWLS 2002: 115-120
9 Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton: Topologically Constrained Logic Synthesis. IWLS 2002: 13-20
8 Alan Mishchenko, Robert K. Brayton: A Boolean Paradigm in Multi-Valued Logic Synthesis. IWLS 2002: 173-177
7 Alan Mishchenko, Marek A. Perkowski: Logic Synthesis of Reversible Wave Cascades. IWLS 2002: 197-202
6 Alan Mishchenko, Robert K. Brayton: Simplification of Non-Deterministic Multi-Valued Networks. IWLS 2002: 333-338
5 Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton: Reducing Multi-Valued Algebraic Operations to Binary. IWLS 2002: 339-344
2001
4EEAlan Mishchenko, Bernd Steinbach, Marek A. Perkowski: An Algorithm for Bi-Decomposition of Logic Functions. DAC 2001: 103-108
3EEMarek A. Perkowski, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Xiaoyu Song, Anas Al-Rabadi, Bart Massey, Pawel Kerntopf, Andrzej Buller, Lech Józwiak, Alan J. Coppola: Regular Realization of Symmetric Functions Using Reversible Logic. DSD 2001: 245-253
1999
2EEMarek A. Perkowski, Rahul Malvi, Stan Grygiel, Michael Burns, Alan Mishchenko: Graph Coloring Algorithms for Fast Evaluation of Curtis Decompositions. DAC 1999: 225-230
1EEMarek A. Perkowski, Alan Mishchenko, Anatoli N. Chebotarev: Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints. Evolvable Hardware 1999: 129-138

Coauthor Index

1Anas Al-Rabadi [3]
2Robert K. Brayton [5] [6] [8] [9] [11] [12] [13] [17] [18] [21] [23] [24] [25] [27] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [40] [42] [43] [44] [45] [46] [48] [49] [50] [51]
3Andrzej Buller [3]
4Jerry R. Burch [26] [28] [29]
5Michael Burns [2]
6Michael L. Case [43] [46] [48]
7Billy Chan [47] [50]
8Satrajit Chatterjee [23] [30] [31] [32] [33] [34] [36] [40] [44] [45]
9Anatoli N. Chebotarev [1]
10Sungmin Cho [40]
11Malgorzata Chrzanowska-Jeske [3] [14] [16] [22] [26] [28] [29] [35]
12Kevin Chung [47] [50]
13Alan J. Coppola [3] [14] [16]
14Niklas Eén [31] [39]
15M. Gao [11]
16Stan Grygiel [2]
17Chung-Yang Huang [41]
18William N. N. Hung [14] [16]
19Aaron P. Hurst [42] [49]
20Stephen Jang [46] [47] [50] [51]
21Mark Jarvin [50]
22Jie-Hong Roland Jiang [5] [11] [18] [21] [24] [37] [41] [51]
23Yunjian Jiang [11]
24Lech Józwiak [3]
25Timothy Kam [20] [23] [30]
26Andrew A. Kennings [14] [16]
27Pawel Kerntopf [3]
28Victor N. Kravets [48]
29Andreas Kuehlmann [44]
30Chih-Chun Lee [41]
31Yinghua Li [11]
32Rahul Malvi [2]
33Barton C. Massey (Bart Massey) [3]
34Marek A. Perkowski [1] [2] [3] [4] [7]
35Tsutomu Sasao [10] [19]
36Subarnarekha Sinha [9] [11] [12] [29]
37Xiaoyu Song [3] [14] [16]
38Niklas Sörensson [39]
39Bernd Steinbach [4]
40Tiziano Villa [11] [24] [37]
41Xinning Wang [20] [23] [30]
42Dennis Wu [50]
43Nina Yevtushenko [24] [37]
44Jin S. Zhang [26] [28] [29] [35]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)