I-Min Liu

2007
16	EE	Huaizhi Wu, Martin D. F. Wong, I-Min Liu, Yusu Wang: Placement-Proximity-Based Voltage Island Grouping Under Performance Requirement. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1256-1269 (2007)
2006
15	EE	Huaizhi Wu, Martin D. F. Wong, I-Min Liu: Timing-constrained and voltage-island-aware voltage assignment. DAC 2006: 429-432
14	EE	Hung-Ming Chen, I-Min Liu, Martin D. F. Wong: I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2552-2556 (2006)
2005
13		Huaizhi Wu, I-Min Liu, Martin D. F. Wong, Yusu Wang: Post-placement voltage island generation under performance requirement. ICCAD 2005: 309-316
12	EE	Hua Xiang, I-Min Liu, Martin D. F. Wong: Wire Planning with Bounded Over-the-Block Wires. ISQED 2005: 622-627
11	EE	Hung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong: Simultaneous power supply planning and noise avoidance in floorplan design. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 578-587 (2005)
2004
10	EE	Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang: I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. ICCD 2004: 562-567
9	EE	Li-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong, I-Min Liu: A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 141-147 (2004)
2002
8	EE	Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu: A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. DATE 2002: 470-477
2001
7	EE	I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong: Integrated power supply planning and floorplanning. ASP-DAC 2001: 589-594
2000
6	EE	I-Min Liu, Adnan Aziz, D. F. Wong: Meeting Delay Constraints in DSM by Minimal Repeater Insertion. DATE 2000: 436-440
5	EE	I-Min Liu, Adnan Aziz: Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing. ICCD 2000: 209-214
4	EE	I-Min Liu, Tan-Li Chou, Adnan Aziz, D. F. Wong: Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. ISPD 2000: 33-38
3	EE	Hai Zhou, Martin D. F. Wong, I-Min Liu, Adnan Aziz: Simultaneous routing and buffer insertion with restrictions onbuffer locations. IEEE Trans. on CAD of Integrated Circuits and Systems 19(7): 819-824 (2000)
1999
2	EE	Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz: Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. DAC 1999: 96-99
1	EE	I-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou: An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. ICCD 1999: 210-215

Coauthor Index

1	Adnan Aziz	[1] [2] [3] [4] [5] [6] [7]
2	Hung-Ming Chen	[7] [10] [11] [14]
3	Tan-Li Chou	[4] [7]
4	Li-Da Huang	[8] [9] [10] [11]
5	Muzhou Shao	[10]
6	Xiaoping Tang	[8] [9]
7	Yusu Wang	[13] [16]
8	Martin D. F. Wong (D. F. Wong)	[1] [2] [3] [4] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16]
9	Huaizhi Wu	[13] [15] [16]
10	Hua Xiang	[8] [9] [12]
11	Hai Zhou	[1] [2] [3]