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Rupesh S. Shelar

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2008
12EEYifang Liu, Rupesh S. Shelar, Jiang Hu: Delay-optimal simultaneous technology mapping and placement with applications to timing optimization. ICCAD 2008: 101-106
2007
11EERupesh S. Shelar: An efficent clustering algorithm for low power clock tree synthesis. ISPD 2007: 181-188
2006
10EERupesh S. Shelar, Prashant Saxena, Sachin S. Sapatnekar: Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 625-636 (2006)
2005
9EERupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar: An efficient technology mapping algorithm targeting routing congestion under delay constraints. ISPD 2005: 137-144
8EERupesh S. Shelar, Sachin S. Sapatnekar: BDD decomposition for delay oriented pass transistor logic synthesis. IEEE Trans. VLSI Syst. 13(8): 957-970 (2005)
7EERupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang: A predictive distributed congestion metric with application to technology mapping. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 696-710 (2005)
2004
6EERupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang: A predictive distributed congestion metric and its application to technology mapping. ISPD 2004: 210-217
2002
5 Rupesh S. Shelar, Sachin S. Sapatnekar: Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits. IWLS 2002: 209-214
4EERupesh S. Shelar, Sachin S. Sapatnekar: An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. VLSI Design 2002: 87-92
2001
3EERupesh S. Shelar, Sachin S. Sapatnekar: Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits. ICCAD 2001: 449-452
2000
2EERupesh S. Shelar, Sacheendra Nath, Jagmohan S. Nanaware: Parameterized Reusable Component Library Methodology. EUROMICRO 2000: 1410-1415
1999
1EERupesh S. Shelar, Madhav P. Desai, H. Narayanan: Decomposition of Finite State Machines for Area, Delay Minimization. ICCD 1999: 620-625

Coauthor Index

1Madhav P. Desai [1]
2Jiang Hu [12]
3Yifang Liu [12]
4Jagmohan S. Nanaware [2]
5H. Narayanan [1]
6Sacheendra Nath [2]
7Sachin S. Sapatnekar [3] [4] [5] [6] [7] [8] [9] [10]
8Prashant Saxena [6] [7] [9] [10]
9Xinning Wang [6] [7] [9]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)