| 2009 |
|---|
| 175 | EE | Karthik Duraisami,
Enrico Macii,
Massimo Poncino:
Using soft-edge flip-flops to compensate NBTI-induced delay degradation.
ACM Great Lakes Symposium on VLSI 2009: 169-172 |
| 174 | EE | Andrea Calimera,
Enrico Macii,
Massimo Poncino:
NBTI-aware sleep transistor design for reliable power-gating.
ACM Great Lakes Symposium on VLSI 2009: 333-338 |
| 2008 |
|---|
| 173 | | Vijay Narayanan,
Zhiyuan Yan,
Enrico Macii,
Sanjukta Bhanja:
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008
ACM 2008 |
| 172 | EE | Ashoka Visweswara Sathanur,
Antonio Pullini,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Optimal sleep transistor synthesis under timing and area constraints.
ACM Great Lakes Symposium on VLSI 2008: 177-182 |
| 171 | EE | Karthik Duraisami,
Enrico Macii,
Massimo Poncino:
Energy efficiency bounds of pulse-encoded buses.
ACM Great Lakes Symposium on VLSI 2008: 183-188 |
| 170 | EE | Andrea Calimera,
Enrico Macii,
Massimo Poncino,
R. Iris Bahar:
Temperature-insensitive synthesis using multi-vt libraries.
ACM Great Lakes Symposium on VLSI 2008: 5-10 |
| 169 | EE | Santa Di Cataldo,
Elisa Ficarra,
Andrea Acquaviva,
Enrico Macii:
Segmentation of nuclei in cancer tissue images: Contrasting active contours with morphology-based approach.
BIBE 2008: 1-6 |
| 168 | | Santa Di Cataldo,
Elisa Ficarra,
Enrico Macii:
Fully-Automated Segmentation of Tumor Areas in Tissue Confocal Images - Comparison between a Custom Unsupervised and a Supervised SVM Approach.
BIOSIGNALS (1) 2008: 116-123 |
| 167 | EE | Ashoka Visweswara Sathanur,
Antonio Pullini,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
A Scalable Algorithmic Framework for Row-Based Power-Gating.
DATE 2008: 379-384 |
| 166 | EE | Bonesi Stefano,
Davide Bertozzi,
Luca Benini,
Enrico Macii:
Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style.
DATE 2008: 967-972 |
| 165 | EE | Andrea Calimera,
Luca Benini,
Enrico Macii:
Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints.
DATE 2008: 973-978 |
| 164 | EE | Ashoka Visweswara Sathanur,
Andrea Calimera,
Antonio Pullini,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits.
ISCAS 2008: 2761-2764 |
| 163 | EE | Andrea Calimera,
R. Iris Bahar,
Enrico Macii,
Massimo Poncino:
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits.
ISLPED 2008: 217-220 |
| 162 | EE | Ashoka Visweswara Sathanur,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction.
ISLPED 2008: 51-56 |
| 161 | EE | Ashoka Visweswara Sathanur,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating.
PATMOS 2008: 42-51 |
| 160 | EE | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers.
IEEE Trans. VLSI Syst. 16(6): 639-649 (2008) |
| 159 | EE | Enrico Macii:
Editorial.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 1-2 (2008) |
| 158 | EE | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Implementation of a thermal management unit for canceling temperature-dependent clock skew variations.
Integration 41(1): 2-8 (2008) |
| 2007 |
|---|
| 157 | | Hai Zhou,
Enrico Macii,
Zhiyuan Yan,
Yehia Massoud:
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007
ACM 2007 |
| 156 | EE | Andrea Calimera,
Antonio Pullini,
Ashoka Visweswara Sathanur,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology.
ACM Great Lakes Symposium on VLSI 2007: 501-504 |
| 155 | EE | Elena Baralis,
Elisa Ficarra,
Alessandro Fiori,
Enrico Macii:
Gene-Markers Representation for Microarray Data Integration.
BIBE 2007: 1056-1060 |
| 154 | EE | Santa Di Cataldo,
Elisa Ficarra,
Enrico Macii:
Selection of Tumor Areas and Segmentation of Nuclear Membranes in Tissue Confocal Images: A Fully Automated Approach.
BIBM 2007: 390-398 |
| 153 | EE | Gila Kamhi,
Sarah Miller,
Stephen Bailey Mentor,
Wolfgang Nebel,
Y. C. Wong,
Juergen Karmann,
Enrico Macii,
Stephen V. Kosonocky,
Steve Curtis:
Early Power-Aware Design & Validation: Myth or Reality?
DAC 2007: 210-211 |
| 152 | EE | Ashoka Visweswara Sathanur,
Andrea Calimera,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing.
DATE 2007: 1544-1549 |
| 151 | EE | Olga Golubeva,
Mirko Loghi,
Massimo Poncino,
Enrico Macii:
Architectural leakage-aware management of partitioned scratchpad memories.
DATE 2007: 1665-1670 |
| 150 | EE | Karthik Duraisami,
Prassanna Sithambaram,
Ashoka Visweswara Sathanur,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew.
ISCAS 2007: 1061-1064 |
| 149 | EE | Ashoka Visweswara Sathanur,
Antonio Pullini,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Timing-driven row-based power gating.
ISLPED 2007: 104-109 |
| 148 | EE | Simone Medardoni,
Davide Bertozzi,
Enrico Macii:
Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies.
ISLPED 2007: 159-164 |
| 147 | EE | Olga Golubeva,
Mirko Loghi,
Enrico Macii,
Massimo Poncino:
Locality-driven architectural cache sub-banking for leakage energy reduction.
ISLPED 2007: 274-279 |
| 146 | EE | Prassanna Sithambaram,
Alberto Macii,
Enrico Macii:
New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses.
PATMOS 2007: 232-241 |
| 145 | EE | Enrico Macii:
Editorial.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 1 (2007) |
| 144 | EE | Gustavo de Veciana,
Marcello Lajolo,
Chen He,
Enrico Macii,
Sachin S. Sapatnekar:
In Memoriam: Margarida F. Jacome.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1549-1550 (2007) |
| 2006 |
|---|
| 143 | EE | Kimish Patel,
Luca Benini,
Enrico Macii,
Massimo Poncino:
STV-Cache: a leakage energy-efficient architecture for data caches.
ACM Great Lakes Symposium on VLSI 2006: 404-409 |
| 142 | EE | Elisa Ficarra,
Enrico Macii,
Giovanni De Micheli,
Luca Benini:
Computer-Aided Evaluation of Protein Expression in Pathological Tissue Images.
CBMS 2006: 413-418 |
| 141 | EE | Enrico Macii,
Massoud Pedram,
Dirk Friebel,
Robert C. Aitken,
Antun Domic,
Roberto Zafalon:
Low-power design tools: are EDA vendors taking this matter seriously?
DATE 2006: 1227 |
| 140 | EE | Ashutosh Chakraborty,
Prassanna Sithambaram,
Karthik Duraisami,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Thermal resilient bounded-skew clock tree optimization methodology.
DATE 2006: 832-837 |
| 139 | EE | Pietro Babighian,
Luca Benini,
Alberto Macii,
Enrico Macii:
Enabling fine-grain leakage management by voltage anchor insertion.
DATE 2006: 868-873 |
| 138 | EE | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits.
ISCAS 2006 |
| 137 | EE | A. Nurrachmat,
Enrico Macii,
Massimo Poncino:
Low-energy pixel approximation for DVI-based LCD interfaces.
ISCAS 2006 |
| 136 | EE | Christine Nardini,
Daniele Masotti,
Sungroh Yoon,
Enrico Macii,
Michael D. Kuo,
Giovanni De Micheli,
Luca Benini:
Mining Gene Sets for Measuring Similarities.
ISCC 2006: 227-232 |
| 135 | EE | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Dynamic thermal clock skew compensation using tunable delay buffers.
ISLPED 2006: 162-167 |
| 134 | EE | Ashutosh Chakraborty,
Karthik Duraisami,
Ashoka Visweswara Sathanur,
Prassanna Sithambaram,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective.
PATMOS 2006: 214-224 |
| 133 | EE | Kimish Patel,
Luca Benini,
Enrico Macii,
Massimo Poncino:
Reducing Conflict Misses by Application-Specific Reconfigurable Indexing.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2626-2637 (2006) |
| 132 | EE | Daniele Masotti,
Elisa Ficarra,
Enrico Macii,
Luca Benini:
Optimized Technique for Dna Structural Properties Discovering.
International Journal on Artificial Intelligence Tools 15(5): 695-710 (2006) |
| 131 | EE | Labros Bisdounis,
Spyros Blionas,
Enrico Macii,
Spiridon Nikolaidis,
Roberto Zafalon:
Implementation Strategy and Results of an Energy-Aware System-on-Chip for 5 GHz WLAN Applications.
J. Low Power Electronics 2(1): 18-26 (2006) |
| 130 | EE | Kimish Patel,
Enrico Macii,
Massimo Poncino,
Luca Benini:
Energy-Efficient Value Based Selective Refresh for Embedded DRAMS.
J. Low Power Electronics 2(1): 70-79 (2006) |
| 129 | EE | Simona Rossi,
Daniele Masotti,
Christine Nardini,
Elena Bonora,
Giovanni Romeo,
Enrico Macii,
Luca Benini,
Stefano Volinia:
TOM: a web-based integrated approach for identification of candidate disease genes.
Nucleic Acids Research 34(Web-Server-Issue): 285-292 (2006) |
| 2005 |
|---|
| 128 | EE | Pietro Babighian,
Luca Benini,
Alberto Macii,
Enrico Macii:
Low-overhead state-retaining elements for low-leakage MTCMOS design.
ACM Great Lakes Symposium on VLSI 2005: 367-370 |
| 127 | EE | Prassanna Sithambaram,
Alberto Macii,
Enrico Macii:
Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMs.
ACM Great Lakes Symposium on VLSI 2005: 377-380 |
| 126 | EE | Kimish Patel,
Enrico Macii,
Massimo Poncino:
Zero clustering: an approach to extend zero compression to instruction caches.
ACM Great Lakes Symposium on VLSI 2005: 56-59 |
| 125 | EE | Andi Nourrachmat,
Sabino Salerno,
Enrico Macii,
Massimo Poncino:
Energy-Efficient Color Approximation for Digital LCD Interfaces.
ICCD 2005: 81-86 |
| 124 | EE | Kimish Patel,
Enrico Macii,
Massimo Poncino:
Frame Buffer Energy Optimization by Pixel Prediction.
ICCD 2005: 98-101 |
| 123 | EE | Labros Bisdounis,
Spyros Blionas,
Enrico Macii,
Spiridon Nikolaidis,
Roberto Zafalon:
Energy-Aware System-on-Chip for 5 GHz Wireless LANs.
PATMOS 2005: 166-176 |
| 122 | EE | Ashutosh Chakraborty,
Enrico Macii,
Massimo Poncino:
Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding.
PATMOS 2005: 297-307 |
| 121 | EE | Kimish Patel,
Luca Benini,
Enrico Macii,
Massimo Poncino:
Energy-Efficient Value-Based Selective Refresh for Embedded DRAMs.
PATMOS 2005: 466-476 |
| 120 | EE | Prassanna Sithambaram,
Alberto Macii,
Enrico Macii:
Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs.
PATMOS 2005: 477-487 |
| 119 | EE | Pietro Babighian,
Luca Benini,
Enrico Macii:
A scalable algorithm for RTL insertion of gated clocks based on ODCs computation.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(1): 29-42 (2005) |
| 118 | EE | Elisa Ficarra,
Luca Benini,
Enrico Macii,
Giampaolo Zuccheri:
Automated DNA fragments recognition and sizing through AFM image processing.
IEEE Transactions on Information Technology in Biomedicine 9(4): 508-517 (2005) |
| 2004 |
|---|
| 117 | | Enrico Macii,
Odysseas G. Koufopavlou,
Vassilis Paliouras:
Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings
Springer 2004 |
| 116 | EE | Alberto Bocca,
Sabino Salerno,
Enrico Macii,
Massimo Poncino:
Energy-efficient bus encoding for LCD displays.
ACM Great Lakes Symposium on VLSI 2004: 240-243 |
| 115 | EE | Daniele Masotti,
Elisa Ficarra,
Enrico Macii,
Luca Benini:
Techniques for Enhancing Computation of DNA Curvature Molecules.
BIBE 2004: 22-29 |
| 114 | EE | Pietro Babighian,
Luca Benini,
Enrico Macii:
A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks.
DATE 2004: 500-505 |
| 113 | EE | Luca Benini,
Alessandro Ivaldi,
Alberto Macii,
Enrico Macii:
Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning.
DATE 2004: 698-699 |
| 112 | EE | Kimish Patel,
Enrico Macii,
Massimo Poncino:
Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC.
DATE 2004: 700-701 |
| 111 | EE | Pietro Babighian,
Luca Benini,
Enrico Macii:
Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating.
DATE 2004: 720-723 |
| 110 | EE | Kimish Patel,
Enrico Macii,
Luca Benini,
Massimo Poncino:
Reducing cache misses by application-specific re-configurable indexing.
ICCAD 2004: 125-130 |
| 109 | | Kimish Patel,
Enrico Macii,
Massimo Poncino:
Energy-performance tradeoffs for the shared memory in multi-processor systems-on-chip.
ISCAS (2) 2004: 361-364 |
| 108 | | Sabino Salerno,
Enrico Macii,
Massimo Poncino:
Crosstalk energy reduction by temporal shielding.
ISCAS (2) 2004: 749-752 |
| 107 | EE | Pietro Babighian,
Luca Benini,
Alberto Macii,
Enrico Macii:
Post-layout leakage power minimization based on distributed sleep transistor insertion.
ISLPED 2004: 138-143 |
| 106 | EE | Sabino Salerno,
Alberto Bocca,
Enrico Macii,
Massimo Poncino:
Limited intra-word transition codes: an energy-efficient bus encoding for LCD display interfaces.
ISLPED 2004: 206-211 |
| 105 | EE | Monica Donno,
Enrico Macii,
Luca Mazzoni:
Power-aware clock tree planning.
ISPD 2004: 138-147 |
| 104 | EE | Sabino Salerno,
Enrico Macii,
Massimo Poncino:
A Low-Power Encoding Scheme for GigaByte Video Interfaces.
PATMOS 2004: 58-68 |
| 103 | EE | Enrico Macii:
RTL power estimation and optimization.
SBCCI 2004: 1 |
| 102 | EE | Enrico Macii:
Leakage power optimization in standard-cell designs.
SBCCI 2004: 7 |
| 101 | | Luca Benini,
Davide Bruni,
Alberto Macii,
Enrico Macii:
Memory energy minimization by data compression: algorithms, architectures and implementation.
IEEE Trans. VLSI Syst. 12(3): 255-268 (2004) |
| 2003 |
|---|
| 100 | | Jorge Juan-Chico,
Enrico Macii:
Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings
Springer 2003 |
| 99 | EE | Luca Benini,
Alberto Macii,
Enrico Macii,
Elvira Omerbegovic,
Massimo Poncino,
Fabrizio Pro:
A novel architecture for power maskable arithmetic units.
ACM Great Lakes Symposium on VLSI 2003: 136-140 |
| 98 | EE | Enrico Macii,
Massimo Poncino,
Sabino Salerno:
Combining wire swapping and spacing for low-power deep-submicron buses.
ACM Great Lakes Symposium on VLSI 2003: 198-202 |
| 97 | EE | Luca Benini,
Alberto Macii,
Enrico Macii,
Elvira Omerbegovic,
Fabrizio Pro,
Massimo Poncino:
Energy-aware design techniques for differential power analysis protection.
DAC 2003: 36-41 |
| 96 | EE | Monica Donno,
Alessandro Ivaldi,
Luca Benini,
Enrico Macii:
Clock-tree power optimization based on RTL clock-gating.
DAC 2003: 622-627 |
| 95 | EE | Alberto Macii,
Enrico Macii,
Massimo Poncino:
Improving the Efficiency of Memory Partitioning by Address Clustering.
DATE 2003: 10018-10023 |
| 94 | EE | Alberto Macii,
Enrico Macii,
Fabrizio Crudo,
Roberto Zafalon:
A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors.
DATE 2003: 10024-10029 |
| 93 | EE | Alberto Macii,
Enrico Macii,
Massimo Poncino:
Increasing the locality of memory access patterns by low-overhead hardware address relocation.
ISCAS (5) 2003: 385-388 |
| 92 | EE | Luca Benini,
Angelo Galati,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Energy-efficient data scrambling on memory-processor interfaces.
ISLPED 2003: 26-29 |
| 91 | EE | Luca Benini,
Davide Bruni,
Alberto Macii,
Enrico Macii:
Hardw are Implementation of Data Compression Algorithms for Memory Energy Optimization.
ISVLSI 2003: 250-251 |
| 90 | EE | B. Arts,
N. van der Eng,
Marc J. M. Heijligers,
H. Munk,
Frans Theeuwen,
Luca Benini,
Enrico Macii,
A. Milia,
Roberto Maro,
A. Bellu:
Statistical Power Estimation of Behavioral Descriptions.
PATMOS 2003: 197-207 |
| 89 | EE | Luca Benini,
Davide Bruni,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Discharge Current Steering for Battery Lifetime Optimization.
IEEE Trans. Computers 52(8): 985-995 (2003) |
| 88 | EE | Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Scheduling battery usage in mobile systems.
IEEE Trans. VLSI Syst. 11(6): 1136-1143 (2003) |
| 2002 |
|---|
| 87 | EE | Monica Donno,
Luca Macchiarulo,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Enhanced clustered voltage scaling for low power.
ACM Great Lakes Symposium on VLSI 2002: 18-23 |
| 86 | EE | Luca Macchiarulo,
Enrico Macii,
Massimo Poncino:
Wire Placement for Crosstalk Energy Minimization in Address Buses.
DATE 2002: 158-162 |
| 85 | EE | Luca Benini,
Davide Bruni,
Alberto Macii,
Enrico Macii:
Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors.
DATE 2002: 449-450 |
| 84 | EE | Luca Benini,
Davide Bruni,
Bruno Riccò,
Alberto Macii,
Enrico Macii:
An adaptive data compression scheme for memory traffic minimization in processor-based systems.
ISCAS (4) 2002: 866-869 |
| 83 | EE | Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Discharge current steering for battery lifetime optimization.
ISLPED 2002: 118-123 |
| 82 | EE | Luca Benini,
Alberto Macii,
Enrico Macii:
Offline Data Profiling Techniques to Enhance Memory Compression in Embedded Systems.
PATMOS 2002: 314-322 |
| 81 | EE | Enrico Macii,
Ingrid Verbauwhede:
Guest editorial: low-power electronics and design.
IEEE Trans. VLSI Syst. 10(2): 69-70 (2002) |
| 80 | EE | Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Minimizing memory access energy in embedded systems by selective instruction compression.
IEEE Trans. VLSI Syst. 10(5): 521-531 (2002) |
| 2001 |
|---|
| 79 | | Enrico Macii,
Vivek De,
Mary Jane Irwin:
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001, Huntington Beach, California, USA, 2001
ACM 2001 |
| 78 | EE | Luca Benini,
Luca Macchiarulo,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip.
DAC 2001: 784-789 |
| 77 | EE | Luca Benini,
Giuliano Castelli,
Alberto Macii,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Extending lifetime of portable systems by battery scheduling.
DATE 2001: 197-203 |
| 76 | EE | Luca Macchiarulo,
Luca Benini,
Enrico Macii:
On-the-fly layout generation for PTL macrocells.
DATE 2001: 546-551 |
| 75 | EE | Luca Macchiarulo,
Enrico Macii,
Massimo Poncino:
Low-energy for deep-submicron address buses.
ISLPED 2001: 176-181 |
| 74 | | Enrico Macii:
Guest Editor's Introduction: Dynamic Power Management of Electronic Systems.
IEEE Design & Test of Computers 18(2): 6-9 (2001) |
| 73 | EE | Lars Kruse,
Eike Schmidt,
Gerd Jochens,
Ansgar Stammermann,
Arne Schulz,
Enrico Macii,
Wolfgang Nebel:
Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs.
IEEE Trans. VLSI Syst. 9(1): 3-14 (2001) |
| 72 | EE | Alberto Macii,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Stream synthesis for efficient power simulation based on spectral transforms.
IEEE Trans. VLSI Syst. 9(3): 417-426 (2001) |
| 71 | EE | Luca Benini,
Giuliano Castelli,
Alberto Macii,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Discrete-time battery models for system-level low-power design.
IEEE Trans. VLSI Syst. 9(5): 630-640 (2001) |
| 70 | EE | Alessandro Bogliolo,
Roberto Corgnati,
Enrico Macii,
Massimo Poncino:
Parameterized RTL power models for soft macros.
IEEE Trans. VLSI Syst. 9(6): 880-887 (2001) |
| 69 | EE | Luca Benini,
Giovanni De Micheli,
Antonio Lioy,
Enrico Macii,
Giuseppe Odasso,
Massimo Poncino:
Synthesis of power-managed sequential components based oncomputational kernel extraction.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1118-1131 (2001) |
| 2000 |
|---|
| 68 | | David Blaauw,
Christian C. Enz,
Thaddeus Gabara,
Enrico Macii:
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000
ACM 2000 |
| 67 | EE | Luca Benini,
Alessandro Bogliolo,
Enrico Macii,
Massimo Poncino,
Mihai Surmei:
Regression-based RTL power models for controllers.
ACM Great Lakes Symposium on VLSI 2000: 147-152 |
| 66 | EE | Luca Benini,
Marco Ferrero,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Supporting system-level power exploration for DSP applications.
ACM Great Lakes Symposium on VLSI 2000: 17-22 |
| 65 | EE | Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Synthesis of application-specific memories for power optimization in embedded systems.
DAC 2000: 300-303 |
| 64 | EE | Luca Benini,
Giuliano Castelli,
Alberto Macii,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
A Discrete-Time Battery Model for High-Level Power Estimation.
DATE 2000: 35- |
| 63 | EE | Roberto Zafalon,
Massimo Rossello,
Enrico Macii,
Massimo Poncino:
Power Macromodeling for a High Quality RT-Level Power Estimation.
ISQED 2000: 59- |
| 62 | EE | Luca Benini,
Giuliano Castelli,
Alberto Macii,
Enrico Macii,
Riccardo Scarsi:
Battery-Driven Dynamic Power Management of Portable Systems.
ISSS 2000: 25-33 |
| 61 | EE | Alessandro Bogliolo,
Enrico Macii,
Virgil Mihailovici,
Massimo Poncino:
Power Models for Semi-autonomous RTL Macros.
PATMOS 2000: 14-23 |
| 60 | EE | Crina Anton,
Pierluigi Civera,
Ionel Colonescu,
Enrico Macii,
Massimo Poncino,
Alessandro Bogliolo:
RTL Estimation of Steering Logic Power.
PATMOS 2000: 36-46 |
| 59 | EE | R. Iris Bahar,
Ernest T. Lampe,
Enrico Macii:
Power optimization of technology-dependent circuits based on symbolic computation of logic implications.
ACM Trans. Design Autom. Electr. Syst. 5(3): 267-293 (2000) |
| 58 | EE | Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Increasing Energy Efficiency of Embedded Systems by Application-Specific Memory Hierarchy Generation.
IEEE Design & Test of Computers 17(2): 74-85 (2000) |
| 57 | EE | Luca Benini,
Giovanni De Micheli,
Alberto Macii,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Glitch power minimization by selective gate freezing.
IEEE Trans. VLSI Syst. 8(3): 287-298 (2000) |
| 56 | EE | Luca Benini,
Giovanni De Micheli,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
A multilevel engine for fast power simulation of realistic inputstreams.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(4): 459-472 (2000) |
| 55 | EE | Fabrizio Ferrandi,
Franco Fummi,
Enrico Macii,
Massimo Poncino,
Donatella Sciuto:
Symbolic optimization of interacting controllers based onredundancy identification and removal.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(7): 760-772 (2000) |
| 1999 |
|---|
| 54 | EE | Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses.
DAC 1999: 128-133 |
| 53 | EE | Luca Benini,
Giovanni De Micheli,
Enrico Macii,
Giuseppe Odasso,
Massimo Poncino:
Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms.
DAC 1999: 247-252 |
| 52 | EE | Luca Benini,
Giovanni De Micheli,
Alberto Macii,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Glitch Power Minimization by Gate Freezing.
DATE 1999: 163-167 |
| 51 | EE | Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Region Compression: A New Scheme for Memory Energy Minimization in Embedded Systems.
EUROMICRO 1999: 1311-1317 |
| 50 | EE | Alberto Macii,
Enrico Macii,
Giuseppe Odasso,
Massimo Poncino,
Riccardo Scarsi:
Regression-Based Macromodeling for Delay Estimation of Behavioral Components.
Great Lakes Symposium on VLSI 1999: 188-191 |
| 49 | EE | Roberto Corgnati,
Enrico Macii,
Massimo Poncino:
Clustered Table-Based Macromodels for RTL Power Estimation.
Great Lakes Symposium on VLSI 1999: 354-357 |
| 48 | EE | Alessandro Bogliolo,
Roberto Corgnati,
Enrico Macii,
Massimo Poncino:
Parameterized RTL power models for combinational soft macros.
ICCAD 1999: 284-288 |
| 47 | EE | Luca Benini,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Selective instruction compression for memory energy reduction in embedded systems.
ISLPED 1999: 206-211 |
| 46 | EE | Luca Benini,
Giovanni De Micheli,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers.
ACM Trans. Design Autom. Electr. Syst. 4(4): 351-375 (1999) |
| 45 | | Luca Benini,
Giovanni De Micheli,
Antonio Lioy,
Enrico Macii,
Giuseppe Odasso,
Massimo Poncino:
Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting.
IEEE Trans. Computers 48(8): 769-779 (1999) |
| 1998 |
|---|
| 44 | EE | Balakrishna Kumthekar,
Luca Benini,
Enrico Macii,
Fabio Somenzi:
In-Place Power Optimization for LUT-Based FPGAs.
DAC 1998: 718-721 |
| 43 | EE | Luca Benini,
Giovanni De Micheli,
Antonio Lioy,
Enrico Macii,
Giuseppe Odasso,
Massimo Poncino:
Computational Kernels and their Application to Sequential Power Optimization.
DAC 1998: 764-769 |
| 42 | EE | Fabrizio Ferrandi,
Franco Fummi,
Enrico Macii,
Massimo Poncino:
Power Estimation of Behavioral Descriptions.
DATE 1998: 762-766 |
| 41 | EE | Luca Benini,
Giovanni De Micheli,
Donatella Sciuto,
Enrico Macii,
Cristina Silvano:
Address Bus Encoding Techniques for System-Level Power Optimization.
DATE 1998: 861- |
| 40 | EE | Luca Benini,
Giovanni De Micheli,
Antonio Lioy,
Enrico Macii,
Giuseppe Odasso,
Massimo Poncino:
Timed Supersetting and the Synthesis of Telescopic Units.
Great Lakes Symposium on VLSI 1998: 331-337 |
| 39 | EE | Luca Benini,
Giovanni De Micheli,
Alberto Macii,
Enrico Macii,
Massimo Poncino:
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding.
Great Lakes Symposium on VLSI 1998: 8-12 |
| 38 | EE | Fabrizio Ferrandi,
Alberto Macii,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi,
Fabio Somenzi:
Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits.
ICCAD 1998: 235-241 |
| 37 | EE | Alberto Macii,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Stream synthesis for efficient power simulation based on spectral transforms.
ISLPED 1998: 30-35 |
| 36 | EE | Luca Benini,
Giovanni De Micheli,
Enrico Macii,
Massimo Poncino,
Stefano Quer:
Power optimization of core-based systems by address bus encoding.
IEEE Trans. VLSI Syst. 6(4): 554-562 (1998) |
| 35 | EE | Enrico Macii,
Massoud Pedram,
Fabio Somenzi:
High-level power modeling, estimation, and optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(11): 1061-1079 (1998) |
| 34 | EE | Luca Benini,
Enrico Macii,
Massimo Poncino,
Giovanni De Micheli:
Telescopic units: a new paradigm for performance optimization of VLSI designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(3): 220-232 (1998) |
| 1997 |
|---|
| 33 | EE | Luca Benini,
Enrico Macii,
Massimo Poncino:
Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control.
DAC 1997: 22-27 |
| 32 | EE | Enrico Macii,
Massoud Pedram,
Fabio Somenzi:
High-Level Power Modeling, Estimation, and Optimization.
DAC 1997: 504-511 |
| 31 | EE | Luca Benini,
Giovanni De Micheli,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks.
ED&TC 1997: 514-520 |
| 30 | EE | Antonio Lioy,
Enrico Macii,
Massimo Poncino,
Massimo Rossello:
Accurate Entropy Calculation for Large Logic Circuits Based on Output Clustering.
Great Lakes Symposium on VLSI 1997: 70- |
| 29 | EE | Luca Benini,
Giovanni De Micheli,
Enrico Macii,
Donatella Sciuto,
Cristina Silvano:
Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems.
Great Lakes Symposium on VLSI 1997: 77-82 |
| 28 | EE | Luca Benini,
Giovanni De Micheli,
Enrico Macii,
Massimo Poncino,
Riccardo Scarsi:
Fast power estimation for deterministic input streams.
ICCAD 1997: 494-501 |
| 27 | EE | Luca Benini,
Giovanni De Micheli,
Enrico Macii,
Massimo Poncino,
Stefano Quer:
System-level power optimization of special purpose applications: the beach solution.
ISLPED 1997: 24-29 |
| 26 | | R. Iris Bahar,
Erica A. Frohm,
Charles M. Gaona,
Gary D. Hachtel,
Enrico Macii,
Abelardo Pardo,
Fabio Somenzi:
Algebraic Decision Diagrams and Their Applications.
Formal Methods in System Design 10(2/3): 171-206 (1997) |
| 25 | EE | Fabrizio Ferrandi,
Franco Fummi,
Donatella Sciuto,
Enrico Macii,
Massimo Poncino:
Testing Core-Based Systems: A Symbolic Methodology.
IEEE Design & Test of Computers 14(4): 69-77 (1997) |
| 24 | EE | R. Iris Bahar,
Hyunwoo Cho,
Gary D. Hachtel,
Enrico Macii,
Fabio Somenzi:
Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1101-1115 (1997) |
| 23 | EE | Enrico Macii,
Bernard Plessier,
Fabio Somenzi:
Formal verification of digital systems by automatic reduction of data paths.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1136-1156 (1997) |
| 1996 |
|---|
| 22 | EE | Fabrizio Ferrandi,
Franco Fummi,
Enrico Macii,
Massimo Poncino,
Donatella Sciuto:
Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques.
DAC 1996: 467-470 |
| 21 | EE | Enrico Macii,
Massimo Poncino:
Exact Computation of the Entropy of a Logic Circuit.
Great Lakes Symposium on VLSI 1996: 162-167 |
| 20 | EE | Fabrizio Ferrandi,
Franco Fummi,
Enrico Macii,
Massimo Poncino,
Donatella Sciuto:
Test Generation for Networks of Interacting FSMs Using Symbolic Techniques.
Great Lakes Symposium on VLSI 1996: 208-213 |
| 19 | EE | Gianpiero Cabodi,
Luciano Lavagno,
Enrico Macii,
Massimo Poncino,
Stefano Quer,
Paolo Camurati,
Ellen Sentovich:
Enhancing FSM Traversal by Temporary Re-Encoding.
ICCD 1996: 6-11 |
| 18 | EE | R. Iris Bahar,
M. Burns,
Gary D. Hachtel,
Enrico Macii,
H. Shin,
Fabio Somenzi:
Symbolic computation of logic implications for technology-dependent low-power synthesis.
ISLPED 1996: 163-168 |
| 17 | EE | Hyunwoo Cho,
Gary D. Hachtel,
Enrico Macii,
Massimo Poncino,
Fabio Somenzi:
Automatic state space decomposition for approximate FSM traversal based on circuit analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1451-1464 (1996) |
| 16 | EE | Hyunwoo Cho,
Gary D. Hachtel,
Enrico Macii,
Bernard Plessier,
Fabio Somenzi:
Algorithms for approximate FSM traversal based on state space decomposition.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1465-1478 (1996) |
| 15 | EE | Gary D. Hachtel,
Enrico Macii,
Abelardo Pardo,
Fabio Somenzi:
Markovian analysis of large finite state machines.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1479-1493 (1996) |
| 1995 |
|---|
| 14 | EE | Srilatha Manne,
Abelardo Pardo,
R. Iris Bahar,
Gary D. Hachtel,
Fabio Somenzi,
Enrico Macii,
Massimo Poncino:
Computing the Maximum Power Cycles of a Sequential Circuit.
DAC 1995: 23-28 |
| 13 | EE | Enrico Macii,
Massimo Poncino:
Predicting the functional complexity of combinational circuits by symbolic spectral analysis of Boolean functions.
EURO-DAC 1995: 294-299 |
| 12 | EE | Enrico Macii,
Massimo Poncino:
Using symbolic Rademacher-Walsh spectral transforms to evaluate the correlation between Boolean functions.
Great Lakes Symposium on VLSI 1995: 112- |
| 11 | EE | Enrico Macii,
Massimo Poncino:
Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks.
Great Lakes Symposium on VLSI 1995: 60-65 |
| 1994 |
|---|
| 10 | EE | Gary D. Hachtel,
Enrico Macii,
Abelardo Pardo,
Fabio Somenzi:
Probabilistic Analysis of Large Finite State Machines.
DAC 1994: 270-275 |
| 9 | | Hyunwoo Cho,
Gary D. Hachtel,
Enrico Macii,
Massimo Poncino,
Fabio Somenzi:
A State Space Decomposition Algorithm for Approximate FSM Traversal.
EDAC-ETC-EUROASIC 1994: 137-141 |
| 8 | | Gary D. Hachtel,
Enrico Macii,
Abelardo Pardo,
Fabio Somenzi:
Symbolic Algorithms to Calculate Steady-State Probabilities of a Finite State Machine.
EDAC-ETC-EUROASIC 1994: 214-218 |
| 7 | | R. Iris Bahar,
Hyunwoo Cho,
Gary D. Hachtel,
Enrico Macii,
Fabio Somenzi:
Timing Analysis of Combinational Circuits using ADD's.
EDAC-ETC-EUROASIC 1994: 625-629 |
| 6 | EE | R. Iris Bahar,
Gary D. Hachtel,
Enrico Macii,
Fabio Somenzi:
A symbolic method to reduce power consumption of circuits containing false paths.
ICCAD 1994: 368-371 |
| 5 | | Hyunwoo Cho,
Gary D. Hachtel,
Enrico Macii,
Massimo Poncino,
Fabio Somenzi:
A Structural Approach to State Space Decomposition for Approximate Reachability Analysis.
ICCD 1994: 236-239 |
| 4 | EE | Enrico Macii,
Angelo R. Meo:
A test generation program for sequential circuits.
J. Electronic Testing 5(1): 115-119 (1994) |
| 1993 |
|---|
| 3 | EE | Hyunwoo Cho,
Gary D. Hachtel,
Enrico Macii,
Bernard Plessier,
Fabio Somenzi:
Algorithms for Approximate FSM Traversal.
DAC 1993: 25-30 |
| 2 | EE | R. Iris Bahar,
Erica A. Frohm,
Charles M. Gaona,
Gary D. Hachtel,
Enrico Macii,
Abelardo Pardo,
Fabio Somenzi:
Algebraic decision diagrams and their applications.
ICCAD 1993: 188-191 |
| 1992 |
|---|
| 1 | EE | Enrico Macii,
Bernard Plessier,
Fabio Somenzi:
Verification of systems containing counters.
ICCAD 1992: 179-182 |
