2009 |
42 | EE | Ying Zhou,
Rouwaida Kanj,
Kanak Agarwal,
Zhuo Li,
Rajiv V. Joshi,
Sani R. Nassif,
Weiping Shi:
The impact of BEOL lithography effects on the SRAM cell performance and yield.
ISQED 2009: 607-612 |
41 | EE | Zhuo Li,
Li-Juan Xing,
Xin-Mei Wang:
A family of asymptotically good quantum codes based on code concatenation
CoRR abs/0901.0042: (2009) |
2008 |
40 | EE | Michael D. Moffitt,
David A. Papa,
Zhuo Li,
Charles J. Alpert:
Path smoothing via discrete optimization.
DAC 2008: 724-727 |
39 | EE | Shiyan Hu,
Zhuo Li,
Charles J. Alpert:
A polynomial time approximation scheme for timing constrained minimum cost layer assignment.
ICCAD 2008: 112-115 |
38 | EE | Tao Luo,
David A. Papa,
Zhuo Li,
Chin-Ngai Sze,
Charles J. Alpert,
David Z. Pan:
Pyramids: an efficient computational geometry-based approach for timing-driven placement.
ICCAD 2008: 204-211 |
37 | EE | David A. Papa,
Tao Luo,
Michael D. Moffitt,
Chin-Ngai Sze,
Zhuo Li,
Gi-Joon Nam,
Charles J. Alpert,
Igor L. Markov:
RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm.
ISPD 2008: 2-9 |
36 | EE | Zhuo Li,
Charles J. Alpert,
Shiyan Hu,
Tuhin Muhmud,
Stephen T. Quay,
Paul G. Villarrubia:
Fast interconnect synthesis with layer assignment.
ISPD 2008: 71-77 |
35 | EE | Rouwaida Kanj,
Zhuo Li,
Rajiv V. Joshi,
Frank Liu,
Sani R. Nassif:
A Root-Finding Method for Assessing SRAM Stability.
ISQED 2008: 804-809 |
34 | EE | Xue Zhang,
Zhuo Li,
Sanglu Lu,
Daoxu Chen,
Xining Li:
Proportion-Integral Power Control for Wireless Ad Hoc Networks.
WCNC 2008: 2289-2294 |
33 | EE | David A. Papa,
Tao Luo,
Michael D. Moffitt,
Chin-Ngai Sze,
Zhuo Li,
Gi-Joon Nam,
Charles J. Alpert,
Igor L. Markov:
RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2156-2168 (2008) |
32 | EE | Zhenheng Li,
Zhuo Li,
You'an Cao:
Representations of the symplectic rook Monoid.
IJAC 18(5): 837-852 (2008) |
31 | EE | Cai-Yun Geng,
Ji-Lai Li,
Xu-Ri Huang,
Hui-Ling Liu,
Zhuo Li,
Chia-Chung Sun:
Theoretical elucidation of the rhodium-catalyzed [4 + 2] annulation reactions.
Journal of Computational Chemistry 29(5): 686-693 (2008) |
2007 |
30 | EE | Ying Zhou,
Zhuo Li,
Yuxin Tian,
Weiping Shi,
Frank Liu:
A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects.
ASP-DAC 2007: 450-455 |
29 | EE | Ying Zhou,
Zhuo Li,
Weiping Shi:
Fast Capacitance Extraction in Multilayer, Conformal and Embedded Dielectric using Hybrid Boundary Element Method.
DAC 2007: 835-840 |
28 | EE | Zhuo Li,
Charles J. Alpert,
Stephen T. Quay,
Sachin S. Sapatnekar,
Weiping Shi:
Probabilistic Congestion Prediction with Partial Blockages.
ISQED 2007: 841-846 |
27 | EE | Charles J. Alpert,
Shrirang K. Karandikar,
Zhuo Li,
Gi-Joon Nam,
Stephen T. Quay,
Haoxing Ren,
Cliff C. N. Sze,
Paul G. Villarrubia,
Mehmet Can Yildiz:
The nuts and bolts of physical synthesis.
SLIP 2007: 89-94 |
26 | EE | Zhuo Li,
Weiping Shi:
An O(bn^2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types
CoRR abs/0710.4691: (2007) |
25 | EE | Shiyan Hu,
Charles J. Alpert,
Jiang Hu,
Shrirang K. Karandikar,
Zhuo Li,
Weiping Shi,
Chin-Ngai Sze:
Fast Algorithms for Slew-Constrained Minimum Cost Buffering.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2009-2022 (2007) |
24 | EE | Zhuo Li,
Ying Zhou,
Weiping Shi:
Wire Sizing for Non-Tree Topology.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 872-880 (2007) |
2006 |
23 | EE | Zhuo Li,
Weiping Shi:
An O(mn) time algorithm for optimal buffer insertion of nets with m sinks.
ASP-DAC 2006: 320-325 |
22 | EE | Mandar Waghmode,
Zhuo Li,
Weiping Shi:
Buffer insertion in large circuits with constructive solution search techniques.
DAC 2006: 296-301 |
21 | EE | Shiyan Hu,
Charles J. Alpert,
Jiang Hu,
Shrirang K. Karandikar,
Zhuo Li,
Weiping Shi,
Cliff C. N. Sze:
Fast algorithms for slew constrained minimum cost buffering.
DAC 2006: 308-313 |
20 | EE | Zhanyuan Jiang,
Shiyan Hu,
Jiang Hu,
Zhuo Li,
Weiping Shi:
A new RLC buffer insertion algorithm.
ICCAD 2006: 553-557 |
19 | EE | Zhenheng Li,
Zhuo Li,
You'an Cao:
Enumeration of symplectic and orthogonal injective partial transformations.
Discrete Mathematics 306(15): 1781-1787 (2006) |
18 | EE | Zhuo Li,
Weiping Shi:
An O(bn/sup 2/) time algorithm for optimal buffer insertion with b buffer types.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 484-489 (2006) |
2005 |
17 | EE | Zhuo Li,
Cliff C. N. Sze,
Charles J. Alpert,
Jiang Hu,
Weiping Shi:
Making fast buffer insertion even faster via approximation techniques.
ASP-DAC 2005: 13-18 |
16 | EE | Zhuo Li,
Weiping Shi:
An O(bn2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types.
DATE 2005: 1324-1329 |
15 | EE | Sani R. Nassif,
Zhuo Li:
A More Effective CEFF.
ISQED 2005: 648-653 |
14 | EE | Xiang Lu,
Zhuo Li,
Wangqi Qiu,
D. M. H. Walker,
Weiping Shi:
Longest-path selection for delay test under process variation.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(12): 1924-1929 (2005) |
13 | EE | Weiping Shi,
Zhuo Li:
A fast algorithm for optimal buffer insertion.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 879-891 (2005) |
2004 |
12 | EE | Weiping Shi,
Zhuo Li,
Charles J. Alpert:
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost.
ASP-DAC 2004: 609-614 |
11 | EE | Xiang Lu,
Zhuo Li,
Wangqi Qiu,
D. M. H. Walker,
Weiping Shi:
Longest path selection for delay test under process variation.
ASP-DAC 2004: 98-103 |
10 | | Zhuo Li,
Kin-Man Lam,
Lansun Shen:
Rate control for MPEG-4 FGS coded video using piecewise rate distortion model.
ICME 2004: 153-156 |
9 | EE | Xiang Lu,
Zhuo Li,
Wangqi Qiu,
D. M. H. Walker,
Weiping Shi:
PARADE: PARAmetric Delay Evaluation under Process Variation.
ISQED 2004: 276-280 |
8 | EE | Wangqi Qiu,
Jing Wang,
D. M. H. Walker,
Divya Reddy,
Zhuo Li,
Weiping Shi,
Hari Balachandran:
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits.
ITC 2004: 223-231 |
7 | EE | Xiang Lu,
Zhuo Li,
Wangqi Qiu,
D. M. H. Walker,
Weiping Shi:
A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide.
MTV 2004: 97-102 |
6 | EE | Wangqi Qiu,
Xiang Lu,
Jing Wang,
Zhuo Li,
D. M. H. Walker,
Weiping Shi:
A Statistical Fault Coverage Metric for Realistic Path Delay Faults.
VTS 2004: 37-42 |
2003 |
5 | EE | Weiping Shi,
Zhuo Li:
An O(nlogn) time algorithm for optimal buffer insertion.
DAC 2003: 580-585 |
4 | EE | Wangqi Qiu,
Xiang Lu,
Zhuo Li,
D. M. H. Walker,
Weiping Shi:
CodSim -- A Combined Delay Fault Simulator.
DFT 2003: 79- |
3 | EE | Zhuo Li,
Xiang Lu,
Weiping Shi:
Process variation dimension reduction based on SVD.
ISCAS (4) 2003: 672-675 |
2 | EE | Zhuo Li,
Xiang Lu,
Wangqi Qiu,
Weiping Shi,
D. M. H. Walker:
A Circuit Level Fault Model for Resistive Opens and Bridges.
VTS 2003: 379-384 |
1 | EE | Zhuo Li,
Xiang Lu,
Wangqi Qiu,
Weiping Shi,
D. M. H. Walker:
A circuit level fault model for resistive bridges.
ACM Trans. Design Autom. Electr. Syst. 8(4): 546-559 (2003) |