Vishal Khandelwal

2008
21	EE	Vishal Khandelwal, Ankur Srivastava: Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 610-620 (2008)
2007
20	EE	Vishal Khandelwal, Ankur Srivastava: Monte-Carlo driven stochastic optimization framework for handling fabrication variability. ICCAD 2007: 105-110
19	EE	Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak: Statistical timing analysis using Kernel smoothing. ICCD 2007: 97-102
18	EE	Vishal Khandelwal, Ankur Srivastava: Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation. ISPD 2007: 11-18
17	EE	Ashish Dobhal, Vishal Khandelwal, Ankur Srivastava: Efficient and Accurate Statistical Timing Analysis for Non-Linear Non-Gaussian Variability With Incremental Attributes. VLSI Design 2007: 259-264
16	EE	Ashish Dobhal, Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava: Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence. VLSI Design 2007: 571-576
15	EE	Vishal Khandelwal, Ankur Srivastava: A Quadratic Modeling-Based Framework for Accurate Statistical Timing Analysis Considering Correlations. IEEE Trans. VLSI Syst. 15(2): 206-215 (2007)
14	EE	Vishal Khandelwal, Ankur Srivastava: Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1246-1255 (2007)
13	EE	Vishal Khandelwal, Ankur Srivastava: Active mode leakage reduction using fine-grained forward body biasing strategy. Integration 40(4): 561-570 (2007)
2006
12	EE	Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava: Probabilistic Evaluation of Solutions in Variability-Driven Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 3010-3016 (2006)
11	EE	Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak: A statistical methodology for wire-length prediction. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1327-1336 (2006)
2005
10	EE	Vishal Khandelwal, Ankur Srivastava: A general framework for accurate statistical timing analysis considering correlations. DAC 2005: 89-94
9	EE	Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava: Simultaneous V/sub t/ selection and assignment for leakage optimization. IEEE Trans. VLSI Syst. 13(6): 762-765 (2005)
2004
8	EE	Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava: High level techniques for power-grid noise immunity. ACM Great Lakes Symposium on VLSI 2004: 13-18
7	EE	Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava: Variability inspired implementation selection problem. ICCAD 2004: 423-427
6	EE	Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava: Efficient statistical timing analysis through error budgeting. ICCAD 2004: 473-477
5	EE	Vishal Khandelwal, Ankur Srivastava: Leakage control through fine-grained placement and sizing of sleep transistors. ICCAD 2004: 533-536
4	EE	Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak: Wire-length prediction using statistical techniques. ICCAD 2004: 702-705
3	EE	Vishal Khandelwal, Ankur Srivastava: Active mode leakage reduction using fine-grained forward body biasing strategy. ISLPED 2004: 150-155
2	EE	Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava: Empirical models for net-length probability distribution and applications. IEEE Trans. VLSI Syst. 12(10): 1066-1075 (2004)
2003
1	EE	Vishal Khandelwal, Azadeh Davoodi, Akash Nanavati, Ankur Srivastava: A Probabilistic Approach to Buffer Insertion. ICCAD 2003: 560-567

Coauthor Index

1	Azadeh Davoodi	[1] [2] [4] [6] [7] [8] [9] [11] [12] [16] [19]
2	Ashish Dobhal	[16] [17]
3	Akash Nanavati	[1]
4	Miodrag Potkonjak	[4] [11] [19]
5	Ankur Srivastava	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21]
6	Jennifer L. Wong	[4] [11] [19]