| 2009 |
|---|
| 150 | EE | Meikang Qiu,
Hao Li,
Edwin Hsing-Mean Sha:
Heterogeneous real-time embedded software optimization considering hardware platform.
SAC 2009: 1637-1641 |
| 149 | EE | Meikang Qiu,
Edwin Hsing-Mean Sha:
Cost minimization while satisfying hard/soft timing constraints for heterogeneous embedded systems.
ACM Trans. Design Autom. Electr. Syst. 14(2): (2009) |
| 148 | EE | Kevin F. Chen,
Edwin Hsing-Mean Sha,
Si-Qing Zheng:
Fast and noniterative scheduling in input-queued switches: Supporting QoS.
Computer Communications 32(5): 834-846 (2009) |
| 147 | EE | Chun Jason Xue,
Zili Shao,
Meilin Liu,
Mei Kang Qiu,
Edwin Hsing-Mean Sha:
Optimizing parallelism for nested loops with iterational and instructional retiming.
J. Embedded Computing 3(1): 29-37 (2009) |
| 2008 |
|---|
| 146 | EE | Chun Jason Xue,
Edwin Hsing-Mean Sha,
Zili Shao,
Meikang Qiu:
Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints.
DATE 2008: 1202-1207 |
| 145 | EE | Meikang Qiu,
Jiande Wu,
Chun Jason Xue,
Jingtong Hu,
Wei-Che Tseng,
Edwin Hsing-Mean Sha:
Loop scheduling and assignment to minimize energy while hiding latency for heterogeneous multi-bank memory.
FPL 2008: 459-462 |
| 144 | EE | Meikang Qiu,
Jing Deng,
Edwin Hsing-Mean Sha:
Failure Rate Minimization with Multiple Function Unit Scheduling for Heterogeneous WSNs.
GLOBECOM 2008: 5213-5217 |
| 143 | | Meikang Qiu,
Jiande Wu,
Chun Jason Xue,
Jingtong Hu,
Wei-Che Tseng,
Edwin Hsing-Mean Sha:
QoS for Networked Heterogeneous Real-Time Embedded Systems.
ISCA PDCCS 2008: 135-140 |
| 142 | EE | Chun Jason Xue,
Zhaohui Yuan,
Guoliang Xing,
Zili Shao,
Edwin Hsing-Mean Sha:
Energy Efficient Operating Mode Assignment for Real-Time Tasks in Wireless Embedded Systems.
RTCSA 2008: 237-246 |
| 141 | EE | Jingtong Hu,
Chun Jason Xue,
Meikang Qiu,
Wei-Che Tseng,
Cathy Qun Xu,
Lei Zhang,
Edwin Hsing-Mean Sha:
Minimizing Transferred Data for Code Update on Wireless Sensor Network.
WASA 2008: 349-360 |
| 140 | EE | Meikang Qiu,
Edwin Hsing-Mean Sha,
Meilin Liu,
Man Lin,
Shaoxiong Hua,
Laurence Tianruo Yang:
Energy minimization with loop fusion and multi-functional-unit scheduling for multidimensional DSP.
J. Parallel Distrib. Comput. 68(4): 443-455 (2008) |
| 139 | EE | Qingfeng Zhuge,
Chun Jason Xue,
Meikang Qiu,
Jingtong Hu,
Edwin Hsing-Mean Sha:
Timing optimization via nest-loop pipelining considering code size.
Microprocessors and Microsystems - Embedded Hardware Design 32(7): 351-363 (2008) |
| 138 | EE | Yen-Kuang Chen,
David W. Lin,
John V. McCanny,
Edwin Hsing-Mean Sha:
Guest Editorial: Special Issue on Design and Programming of Signal Processors for Multimedia Communication.
Signal Processing Systems 51(3): 207-208 (2008) |
| 2007 |
|---|
| 137 | | Tei-Wei Kuo,
Edwin Hsing-Mean Sha,
Minyi Guo,
Laurence Tianruo Yang,
Zili Shao:
Embedded and Ubiquitous Computing, International Conference, EUC 2007, Taipei, Taiwan, December 17-20, 2007, Proceedings
Springer 2007 |
| 136 | EE | Meikang Qiu,
Chun Xue,
Zili Shao,
Edwin Hsing-Mean Sha:
Energy minimization with soft real-time and DVS for uniprocessor and multiprocessor embedded systems.
DATE 2007: 1641-1646 |
| 135 | EE | Chun Xue,
Zili Shao,
Meilin Liu,
Qingfeng Zhuge,
Edwin Hsing-Mean Sha:
Parallel Network Intrusion Detection on Reconfigurable Platforms.
EUC 2007: 75-86 |
| 134 | EE | Su Te Lei,
Kang Zhang,
Edwin Hsing-Mean Sha:
Applying Situation Awareness to Mobile Proactive Information Delivery.
EUC Workshops 2007: 592-603 |
| 133 | EE | Meikang Qiu,
Edwin Hsing-Mean Sha:
Energy-Aware Online Algorithm to Satisfy Sampling Rates with Guaranteed Probability for Sensor Applications.
HPCC 2007: 156-167 |
| 132 | EE | Meng Wang,
Zili Shao,
Chun Xue,
Edwin Hsing-Mean Sha:
Real-Time Loop Scheduling with Leakage Energy Minimization for Embedded VLIW DSP Processors.
RTCSA 2007: 12-19 |
| 131 | EE | Bin Xiao,
Jiannong Cao,
Zili Shao,
Qingfeng Zhuge,
Edwin Hsing-Mean Sha:
Analysis and algorithms design for the partition of large-scale adaptive mobile wireless networks.
Computer Communications 30(8): 1899-1912 (2007) |
| 130 | EE | Kevin F. Chen,
Edwin Hsing-Mean Sha:
Universal Routing and Performance Assurance for Distributed Networks.
Journal of Interconnection Networks 8(1): 1-28 (2007) |
| 129 | EE | Meikang Qiu,
Zhiping Jia,
Chun Xue,
Zili Shao,
Edwin Hsing-Mean Sha:
Voltage Assignment with Guaranteed Probability Satisfying Timing Constraint for Real-time Multiproceesor DSP.
VLSI Signal Processing 46(1): 55-73 (2007) |
| 128 | EE | Chun Xue,
Zili Shao,
Edwin Hsing-Mean Sha:
Maximize Parallelism Minimize Overhead for Nested Loops via Loop Striping.
VLSI Signal Processing 47(2): 153-167 (2007) |
| 2006 |
|---|
| 127 | | Edwin Hsing-Mean Sha,
Sung-Kook Han,
Cheng-Zhong Xu,
Moon-hae Kim,
Laurence Tianruo Yang,
Bin Xiao:
Embedded and Ubiquitous Computing, International Conference, EUC 2006, Seoul, Korea, August 1-4, 2006, Proceedings
Springer 2006 |
| 126 | EE | Mei Kang Qiu,
Chun Xue,
Qingfeng Zhuge,
Zili Shao,
Meilin Liu,
Edwin Hsing-Mean Sha:
Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability.
ASAP 2006: 178-181 |
| 125 | EE | Mei Kang Qiu,
Chun Xue,
Zili Shao,
Qingfeng Zhuge,
Meilin Liu,
Edwin Hsing-Mean Sha:
Efficent Algorithm of Energy Minimization for Heterogeneous Wireless Sensor Network.
EUC 2006: 25-34 |
| 124 | EE | Chun Xue,
Zili Shao,
Meilin Liu,
Mei Kang Qiu,
Edwin Hsing-Mean Sha:
Loop Striping: Maximize Parallelism for Nested Loops.
EUC 2006: 405-414 |
| 123 | EE | Chun Xue,
Zili Shao,
Meilin Liu,
Mei Kang Qiu,
Edwin Hsing-Mean Sha:
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture.
ICPADS (1) 2006: 375-382 |
| 122 | | Meilin Liu,
Chun Xue,
Edwin Hsing-Mean Sha:
Optimizing Timing and Code Size Using Maximum Direct Loop Fusion.
ISCA PDCS 2006: 38-43 |
| 121 | EE | Zili Shao,
Bin Xiao,
Chun Xue,
Qingfeng Zhuge,
Edwin Hsing-Mean Sha:
Loop scheduling with timing and switching-activity minimization for VLIW DSP.
ACM Trans. Design Autom. Electr. Syst. 11(1): 165-185 (2006) |
| 120 | EE | Zili Shao,
Chun Xue,
Qingfeng Zhuge,
Mei Kang Qiu,
Bin Xiao,
Edwin Hsing-Mean Sha:
Security Protection and Checking for Embedded System Integration against Buffer Overflow Attacks via Hardware/Software.
IEEE Trans. Computers 55(4): 443-453 (2006) |
| 119 | EE | Chantana Chantrapornchai,
Wanlop Surakampontorn,
Edwin Hsing-Mean Sha:
Design Exploration With Imprecise Latency and Register Constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2650-2662 (2006) |
| 118 | EE | Timothy W. O'Neil,
Edwin Hsing-Mean Sha:
Time-constrained loop scheduling with minimal resources.
J. Embedded Computing 2(1): 103-117 (2006) |
| 117 | EE | Kevin F. Chen,
Edwin Hsing-Mean Sha:
The fat-stack and universal routing in interconnection networks.
J. Parallel Distrib. Comput. 66(5): 705-715 (2006) |
| 116 | EE | Zili Shao,
Jiannong Cao,
Keith C. C. Chan,
Chun Xue,
Edwin Hsing-Mean Sha:
Hardware/software optimization for array & pointer boundary checking against buffer overflow attacks.
J. Parallel Distrib. Comput. 66(9): 1129-1136 (2006) |
| 115 | EE | Qingfeng Zhuge,
Chun Xue,
Zili Shao,
Meilin Liu,
Meikang Qiu,
Edwin Hsing-Mean Sha:
Design optimization and space minimization considering timing and code size via retiming and unfolding.
Microprocessors and Microsystems 30(4): 173-183 (2006) |
| 2005 |
|---|
| 114 | EE | Zili Shao,
Qingfeng Zhuge,
Chun Xue,
Bin Xiao,
Edwin Hsing-Mean Sha:
High-level synthesis for DSP applications using heterogeneous functional units.
ASP-DAC 2005: 302-304 |
| 113 | EE | Chun Xue,
Zili Shao,
Meilin Liu,
Edwin Hsing-Mean Sha:
Iterational retiming: maximize iteration-level parallelism for nested loops.
CODES+ISSS 2005: 309-314 |
| 112 | EE | Meilin Liu,
Qingfeng Zhuge,
Zili Shao,
Chun Xue,
Mei Kang Qiu,
Edwin Hsing-Mean Sha:
Loop Distribution and Fusion with Timing and Code Size Optimization for Embedded DSPs.
EUC 2005: 121-130 |
| 111 | EE | Chun Xue,
Zili Shao,
Meilin Liu,
Mei Kang Qiu,
Edwin Hsing-Mean Sha:
Optimizing Nested Loops with Iterational and Instructional Retiming.
EUC 2005: 164-173 |
| 110 | EE | Edwin Hsing-Mean Sha:
Parallel Embedded Systems: Optimizations and Challenges.
EUC 2005: 2 |
| 109 | | Timothy W. O'Neil,
Edwin Hsing-Mean Sha:
Static Scheduling of Split-Node Data-Flow Graphs.
IASTED PDCS 2005: 125-130 |
| 108 | | Mei Kang Qiu,
Meilin Liu,
Chun Xue,
Qingfeng Zhuge,
Edwin Hsing-Mean Sha,
Zili Shao:
Optimal Assignment with Guaranteed Confidence Probability for Trees on Heterogeneous DSP Systems.
IASTED PDCS 2005: 295-300 |
| 107 | EE | Bin Xiao,
Wei Chen,
Yanxiang He,
Edwin Hsing-Mean Sha:
An Active Detecting Method Against SYN Flooding Attack.
ICPADS (1) 2005: 709-715 |
| 106 | EE | Ying Chen,
Zili Shao,
Qingfeng Zhuge,
Chun Xue,
Bin Xiao,
Edwin Hsing-Mean Sha:
Minimizing Energy via Loop Scheduling and DVS for Multi-Core Embedded Systems.
ICPADS (2) 2005: 2-6 |
| 105 | EE | Kevin F. Chen,
Edwin Hsing-Mean Sha,
Bin Xiao:
Universal Routing in Distributed Networks.
ICPADS (2) 2005: 555-559 |
| 104 | | Kevin F. Chen,
Meilin Liu,
Edwin Hsing-Mean Sha:
A Feasible Baseline Architecture for Building and Evaluating Distributed Systems.
ISCA PDCS 2005: 185-190 |
| 103 | | Meilin Liu,
Zili Shao,
Chun Xue,
Kevin F. Chen,
Edwin Hsing-Mean Sha:
Multi-level Loop Fusion with Minimal Code Size.
ISCA PDCS 2005: 348- |
| 102 | EE | Meilin Liu,
Qingfeng Zhuge,
Zili Shao,
Chun Xue,
Meikang Qiu,
Edwin Hsing-Mean Sha:
Maximum Loop Distribution and Fusion for Two-level Loops Considering Code Size.
ISPAN 2005: 126-131 |
| 101 | EE | Kevin F. Chen,
Edwin Hsing-Mean Sha,
S. Q. Zheng:
A Fast Noniterative Scheduler for Input-Queued Switches with Unbuffered Crossbars.
ISPAN 2005: 230-235 |
| 100 | EE | Zili Shao,
Chun Xue,
Qingfeng Zhuge,
Edwin Hsing-Mean Sha,
Bin Xiao:
Efficient Array & Pointer Bound Checking Against Buffer Overflow Attacks via Hardware/Software.
ITCC (1) 2005: 780-785 |
| 99 | EE | Zili Shao,
Qingfeng Zhuge,
Chun Xue,
Edwin Hsing-Mean Sha:
Efficient Assignment and Scheduling for Heterogeneous DSP Systems.
IEEE Trans. Parallel Distrib. Syst. 16(6): 516-525 (2005) |
| 98 | EE | Timothy W. O'Neil,
Edwin Hsing-Mean Sha:
Combining Extended Retiming and Unfolding for Rate-Optimal Graph Transformation.
VLSI Signal Processing 39(3): 273-293 (2005) |
| 2004 |
|---|
| 97 | EE | Zili Shao,
Qingfeng Zhuge,
Meilin Liu,
Bin Xiao,
Edwin Hsing-Mean Sha:
Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP Applications.
ASAP 2004: 224-234 |
| 96 | EE | Chantana Chantrapornchai,
Wanlop Surakumpolthorn,
Edwin Hsing-Mean Sha:
Design Exploration Framework Under Impreciseness Based on Register-Constrained Inclusion Scheduling.
ASIAN 2004: 78-92 |
| 95 | EE | Meilin Liu,
Qingfeng Zhuge,
Zili Shao,
Edwin Hsing-Mean Sha:
General loop fusion technique for nested loops considering timing and code size.
CASES 2004: 190-201 |
| 94 | EE | Chantana Chantrapornchai,
Wanlop Surakumpolthorn,
Edwin Hsing-Mean Sha:
Efficient Scheduling for Design Exploration with Imprecise Latency and Register Constraints.
EUC 2004: 259-270 |
| 93 | EE | Zili Shao,
Qingfeng Zhuge,
Meilin Liu,
Edwin Hsing-Mean Sha,
Bin Xiao:
Loop Scheduling for Real-Time DSPs with Minimum Switching Activities on Multiple-Functional-Unit Architectures.
EUC 2004: 53-63 |
| 92 | EE | Chun Xue,
Zili Shao,
Edwin Hsing-Mean Sha,
Bin Xiao:
Optimizing Address Assignment for Scheduling Embedded DSPs.
EUC 2004: 64-73 |
| 91 | EE | Bin Xiao,
Jiannong Cao,
Edwin Hsing-Mean Sha:
Maintaining Comprehensive Resource Availability in P2P Networks.
GCC 2004: 543-550 |
| 90 | EE | Qingfeng Zhuge,
Zili Shao,
Edwin Hsing-Mean Sha:
Timing Optimization of Nested Loops Considering Code Size for DSP Applications.
ICPP 2004: 475-482 |
| 89 | EE | Zili Shao,
Qingfeng Zhuge,
Yi He,
Chun Xue,
Meilin Liu,
Edwin Hsing-Mean Sha:
Assignment and Scheduling of Real-time DSP Applications for Heterogeneous Functional Units.
IPDPS 2004 |
| 88 | | Kevin F. Chen,
Edwin Hsing-Mean Sha:
The Fat-Stack and Universal Routing in Interconnection Networks.
ISCA PDCS 2004: 321-326 |
| 87 | | Meilin Liu,
Qingfeng Zhuge,
Zili Shao,
Kevin F. Chen,
Edwin Hsing-Mean Sha:
Loop Fusion via Retiming for DSP Applications.
ISCA PDCS 2004: 403-408 |
| 86 | EE | Bin Xiao,
Jiannong Cao,
Qingfeng Zhuge,
Yi He,
Edwin Hsing-Mean Sha:
Approximation Algorithms Design for Disk Partial Covering Problem.
ISPAN 2004: 104-110 |
| 85 | EE | Bin Xiao,
Jiannong Cao,
Qingfeng Zhuge,
Zili Shao,
Edwin Hsing-Mean Sha:
Dynamic Update of Shortest Path Tree in OSPF.
ISPAN 2004: 18-23 |
| 84 | EE | Zili Shao,
Chun Xue,
Qingfeng Zhuge,
Edwin Hsing-Mean Sha,
Bin Xiao:
Security Protection and Checking in Embedded System Integration Against Buffer Overflow Attacks.
ITCC (1) 2004: 409-413 |
| 83 | | Bin Xiao,
Qingfeng Zhuge,
Edwin Hsing-Mean Sha:
Efficient Algorithms for Dynamic Update of Shortest Path Tree in Networking.
I. J. Comput. Appl. 11(1): 60-75 (2004) |
| 82 | EE | Zili Shao,
Qingfeng Zhuge,
Youtao Zhang,
Edwin Hsing-Mean Sha:
Algorithms and analysis of scheduling for low-power high-performance DSP on VLIW processors.
IJHPCN 1(1/2/3): 4-16 (2004) |
| 81 | EE | David R. Surma,
Edwin Hsing-Mean Sha,
Nelson L. Passos:
Communication Scheduling With Re-Routing Based On Static And Hybrid Techniques.
Journal of Circuits, Systems, and Computers 13(5): 1039-1064 (2004) |
| 2003 |
|---|
| 80 | EE | Zili Shao,
Qingfeng Zhuge,
Yi He,
Edwin Hsing-Mean Sha:
Defending Embedded Systems Against Buffer Overflow via Hardware/Software.
ACSAC 2003: 352-363 |
| 79 | EE | Qingfeng Zhuge,
Zili Shao,
Bin Xiao,
Edwin Hsing-Mean Sha:
Design space minimization with timing and code size optimization for embedded DSP.
CODES+ISSS 2003: 144-149 |
| 78 | | Cathy Qun Xu,
Youtao Zhang,
Edwin Hsing-Mean Sha:
Application-Specific Interconnection Network Design in Clustered DSP Processors.
ISCA PDCS 2003: 69-75 |
| 77 | | Bin Xiao,
Qingfeng Zhuge,
Zili Shao,
Edwin Hsing-Mean Sha:
Design and Analysis of Improved Shortest Path Tree Update for Network Routing.
ISCA PDCS 2003: 82-87 |
| 76 | EE | Zili Shao,
Qingfeng Zhuge,
Edwin Hsing-Mean Sha,
Chantana Chantrapornchai:
Loop scheduling for minimizing schedule length and switching activities.
ISCAS (5) 2003: 109-112 |
| 75 | EE | Qingfeng Zhuge,
Edwin Hsing-Mean Sha,
Chantana Chantrapornchai:
An Integrated Framework of Design Optimization and Space Minimization for DSP applications.
ISCAS (5) 2003: 601-604 |
| 74 | EE | Qingfeng Zhuge,
Bin Xiao,
Edwin Hsing-Mean Sha:
Code size reduction technique and implementation for software-pipelined DSP applications.
ACM Trans. Embedded Comput. Syst. 2(4): 590-613 (2003) |
| 73 | | Edwin Hsing-Mean Sha,
Timothy W. O'Neil,
Nelson L. Passos:
Efficient Polynomial-Time Nested Loop Fusion with Full Parallelism.
I. J. Comput. Appl. 10(1): 9-24 (2003) |
| 2002 |
|---|
| 72 | EE | Timothy W. O'Neil,
Edwin Hsing-Mean Sha:
Minimizing resources in a repeating schedule for a split-node data-flow graph.
ACM Great Lakes Symposium on VLSI 2002: 136-141 |
| 71 | | Bin Xiao,
Qingfeng Zhuge,
Edwin Hsing-Mean Sha,
Chantana Chantrapornchai:
Analysis and Algorithms for Partitioning of Large-scale Adaptive Mobile Networks.
IASTED PDCS 2002: 302-308 |
| 70 | | Timothy W. O'Neil,
Edwin Hsing-Mean Sha:
Unfolding a Split-node Data-flow Graph.
IASTED PDCS 2002: 712-717 |
| 69 | EE | Qingfeng Zhuge,
Zili Shao,
Edwin Hsing-Mean Sha:
Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications.
ICPP 2002: 613-620 |
| 68 | EE | Qingfeng Zhuge,
Bin Xiao,
Edwin Hsing-Mean Sha:
Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP.
IPDPS 2002 |
| 67 | EE | Qingfeng Zhuge,
Bin Xiao,
Edwin Hsing-Mean Sha:
Performance optimization of multiple memory architectures for DSP.
ISCAS (5) 2002: 469-472 |
| 66 | EE | Bin Xiao,
Zili Shao,
Chantana Chantrapornchai,
Edwin Hsing-Mean Sha,
Qingfeng Zhuge:
Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops.
ISSS 2002: 144-149 |
| 2001 |
|---|
| 65 | | Edwin Hsing-Mean Sha:
Proceedings of the ISCA 14th International Conference on Parallel and Distributed Computing Systems, August 8-10, 2001, Richardson, Texas, USA
ISCA 2001 |
| 64 | EE | Zhong Wang,
Edwin Hsing-Mean Sha,
Yuke Wang:
Optimal partitioning and balanced scheduling with the maximal overlap of data footprints.
ACM Great Lakes Symposium on VLSI 2001: 31-36 |
| 63 | EE | Zhong Wang,
Edwin Hsing-Mean Sha,
Xiaobo Hu:
Combined partitioning and data padding for scheduling multiple loop nests.
CASES 2001: 67-75 |
| 62 | | Timothy W. O'Neil,
Edwin Hsing-Mean Sha:
On Retiming Synchronous Data-Flow Graphs.
ISCA PDCS 2001: 103-108 |
| 61 | | Bin Xiao,
Qingfeng Zhuge,
Edwin Hsing-Mean Sha:
Efficient Update of Shortest Path Algorithms for Network Routing.
ISCA PDCS 2001: 315-320 |
| 60 | | Yingtao Jiang,
Yuke Wang,
Edwin Hsing-Mean Sha:
Distributed Scaling Algorithm for FFT Computation Using Fixed-Point Arithmetic.
ISCA PDCS 2001: 490-495 |
| 59 | | Zhong Wang,
Qingfeng Zhuge,
Edwin Hsing-Mean Sha:
Scheduling and partitioning for multiple loop nests.
ISSS 2001: 183-188 |
| 58 | EE | Xiaobo Sharon Hu,
Tao Zhou,
Edwin Hsing-Mean Sha:
Estimating probabilistic timing performance for real-time embedded systems.
IEEE Trans. VLSI Syst. 9(6): 833-844 (2001) |
| 57 | EE | Zhong Wang,
Timothy W. O'Neil,
Edwin Hsing-Mean Sha:
Minimizing Average Schedule Length under Memory Constraints by Optimal Partitioning and Prefetching.
VLSI Signal Processing 27(3): 215-233 (2001) |
| 2000 |
|---|
| 56 | EE | Virgil Andronache,
Edwin Hsing-Mean Sha,
Nelson L. Passos:
Design and analysis of efficient application-specific on-line page replacement techniques.
ACM Great Lakes Symposium on VLSI 2000: 123-128 |
| 55 | EE | Chantana Chantrapornchai,
Edwin Hsing-Mean Sha,
Xiaobo Hu:
Efficient algorithms for acceptable design exploration.
ACM Great Lakes Symposium on VLSI 2000: 139-142 |
| 54 | EE | Zhong Wang,
Michael Kirkpatrick,
Edwin Hsing-Mean Sha:
Optimal two level partitioning and loop scheduling for hiding memory latency for DSP applications.
DAC 2000: 540-545 |
| 53 | EE | Jiangfeng Ding,
Jon C. Furgeson,
Edwin Hsing-Mean Sha:
Application Specific Image Compression for Virtual Conferencing.
ITCC 2000: 48-53 |
| 52 | EE | Sissades Tongsima,
Edwin Hsing-Mean Sha,
Chantana Chantrapornchai,
David R. Surma,
Nelson L. Passos:
Probabilistic Loop Scheduling for Applications with Uncertain Execution Time.
IEEE Trans. Computers 49(1): 65-80 (2000) |
| 51 | EE | Fei Chen,
Timothy W. O'Neil,
Edwin Hsing-Mean Sha:
Optimizing Overall Loop Schedules Using Prefetching and Partitioning.
IEEE Trans. Parallel Distrib. Syst. 11(6): 604-614 (2000) |
| 50 | EE | David R. Surma,
Edwin Hsing-Mean Sha:
Communication Reduction in Multiple Multicasts Based on Hybrid Static-Dynamic Scheduling.
IEEE Trans. Parallel Distrib. Syst. 11(9): 865-878 (2000) |
| 49 | EE | Chantana Chantrapornchai,
Edwin Hsing-Mean Sha,
Xiaobo Sharon Hu:
Efficient design exploration based on module utility selection.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 19-29 (2000) |
| 48 | EE | Sissades Tongsima,
Timothy W. O'Neil,
Chantana Chantrapornchai,
Edwin Hsing-Mean Sha:
Properties and Algorithms for Unfolding of Probabilistic Data-Flow Graphs.
VLSI Signal Processing 25(3): 215-233 (2000) |
| 1999 |
|---|
| 47 | EE | Chantana Chantrapornchai,
Sissades Tongsima,
Edwin Hsing-Mean Sha:
Rapid Prototyping Techniques for Fuzzy Controllers.
ASIAN 1999: 37-49 |
| 46 | EE | Tao Zhou,
Xiaobo Sharon Hu,
Edwin Hsing-Mean Sha:
A probabilistic performance metric for real-time system design.
CODES 1999: 90-94 |
| 45 | EE | Chantana Chantrapornchai,
Edwin Hsing-Mean Sha,
Xiaobo Sharon Hu:
Efficient Algorithms for Finding Highly Acceptable Designs Based on Module-Utility Selections.
Great Lakes Symposium on VLSI 1999: 128-131 |
| 44 | EE | Fei Chen,
Edwin Hsing-Mean Sha:
Loop Scheduling and Partitions for Hiding Memory Latencies.
ISSS 1999: 64-70 |
| 1998 |
|---|
| 43 | EE | Kaisheng Wang,
Ted Zhihong Yu,
Edwin Hsing-Mean Sha:
RCRS: A Framework for Loop Scheduling with Limited Number of Registers.
Great Lakes Symposium on VLSI 1998: 386-391 |
| 42 | EE | Yi Tian,
Edwin Hsing-Mean Sha,
Chantana Chantrapornchai,
Peter M. Kogge:
Optimizing Data Scheduling on Processor-in-Memory Arrays.
IPPS/SPDP 1998: 57-61 |
| 41 | EE | Sissades Tongsima,
Chantana Chantrapornchai,
Edwin Hsing-Mean Sha:
Probabilistic Loop Scheduling Considering Communication Overhead.
JSSPP 1998: 158-179 |
| 40 | EE | Anantha Chandrakasan,
Edwin Hsing-Mean Sha:
Special Section on Low-Power Electronics and Design.
IEEE Trans. VLSI Syst. 6(4): 518-519 (1998) |
| 39 | EE | Nelson L. Passos,
Edwin Hsing-Mean Sha:
Scheduling of uniform multidimensional systems under resource constraints.
IEEE Trans. VLSI Syst. 6(4): 719-730 (1998) |
| 38 | EE | Sissades Tongsima,
Chantana Chantrapornchai,
Edwin Hsing-Mean Sha,
Nelson L. Passos:
Reducing Data Hazards on Multi-pipelined DSP Architecture with Loop Scheduling.
VLSI Signal Processing 18(2): 111-123 (1998) |
| 1997 |
|---|
| 37 | EE | Sissades Tongsima,
Chantana Chantrapornchai,
Edwin Hsing-Mean Sha,
Nelson L. Passos:
Scheduling with Confidence for Probabilistic Data-flow Graphs.
Great Lakes Symposium on VLSI 1997: 150-155 |
| 36 | EE | Ted Zhihong Yu,
Edwin Hsing-Mean Sha,
Nelson L. Passos,
Roy Dz-Ching Ju:
Algorithm and Hardware Support for Branch Anticipation.
Great Lakes Symposium on VLSI 1997: 163- |
| 35 | EE | Sissades Tongsima,
Chantana Chantrapornchai,
Edwin Hsing-Mean Sha,
Nelson L. Passos:
Probabilistic Rotation: Scheduling Graphs with Uncertain Execution Time.
ICPP 1997: 292- |
| 34 | EE | David R. Surma,
Edwin Hsing-Mean Sha:
Hybrid static-dynamic communication scheduling for parallel systems.
SAC 1997: 374-379 |
| 33 | EE | Liang-Fang Chao,
Edwin Hsing-Mean Sha:
Scheduling Data-Flow Graphs via Retiming and Unfolding.
IEEE Trans. Parallel Distrib. Syst. 8(12): 1259-1267 (1997) |
| 32 | EE | Nelson L. Passos,
Edwin Hsing-Mean Sha,
Liang-Fang Chao:
Multidimensional interleaving for synchronous circuit design optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(2): 146-159 (1997) |
| 31 | EE | Liang-Fang Chao,
Andrea S. LaPaugh,
Edwin Hsing-Mean Sha:
Rotation scheduling: a loop pipelining algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 229-239 (1997) |
| 1996 |
|---|
| 30 | EE | David R. Surma,
Edwin Hsing-Mean Sha:
Static Communication Scheduling for Minimizing Collisions in Application Specific Parallel Systems.
ASAP 1996: 240-249 |
| 29 | EE | Michael Sheliga,
Nelson L. Passos,
Edwin Hsing-Mean Sha:
Fully Parallel Hardware/Software Codesign for Multi-Dimensional DSP Applications.
CODES 1996: 18-27 |
| 28 | EE | Chantana Chantrapornchai,
Sissades Tongsima,
Edwin Hsing-Mean Sha:
Rapid Prototyping for Fuzzy Systems.
Great Lakes Symposium on VLSI 1996: 234-239 |
| 27 | EE | Nelson L. Passos,
Edwin Hsing-Mean Sha:
A Parameterized Index-Generator for the Multi-Dimensional Interleaving Optimization.
Great Lakes Symposium on VLSI 1996: 66-71 |
| 26 | EE | Nelson L. Passos,
Edwin Hsing-Mean Sha:
Synthesis of Multi-Dimensional Applications in VHDL.
ICCD 1996: 530- |
| 25 | | Edwin Hsing-Mean Sha,
Chenhua Lang,
Nelson L. Passos:
Polynomial-Time Nested Loop Fusion with Full Parallelism.
ICPP, Vol. 3 1996: 9-16 |
| 24 | | Qingyan Wang,
Nelson L. Passos,
Edwin Hsing-Mean Sha:
Optimal Data Scheduling for Uniform Multidimensional Applications.
IEEE Trans. Computers 45(12): 1439-1444 (1996) |
| 23 | EE | Nelson L. Passos,
Edwin Hsing-Mean Sha:
Achieving Full Parallelism Using Multidimensional Retiming.
IEEE Trans. Parallel Distrib. Syst. 7(11): 1150-1163 (1996) |
| 22 | EE | Michael Sheliga,
Edwin Hsing-Mean Sha:
Hardware/Software co-design with the HMS framework.
VLSI Signal Processing 13(1): 37-56 (1996) |
| 1995 |
|---|
| 21 | EE | Hai Zhao,
Nicole Marie Sabine,
Edwin Hsing-Mean Sha:
Improving self-timed pipeline ring performance through the addition of buffer loops.
Great Lakes Symposium on VLSI 1995: 218-223 |
| 20 | EE | Michael Sheliga,
Edwin Hsing-Mean Sha:
Bus minimization and scheduling of multi-chip systems.
Great Lakes Symposium on VLSI 1995: 40-45 |
| 19 | EE | Nelson L. Passos,
Edwin Hsing-Mean Sha:
Push-up scheduling: Optimal polynomial-time resource constrained scheduling for multi-dimensional applications.
ICCAD 1995: 588-591 |
| 18 | EE | Nelson L. Passos,
Edwin Hsing-Mean Sha,
Liang-Fang Chao:
Multi-dimensional interleaving for time-and-memory design optimization.
ICCD 1995: 440-445 |
| 17 | | Nelson L. Passos,
Edwin Hsing-Mean Sha,
Liang-Fang Chao:
Memory Efficient Fully Parallel Nested Loop Pipelining.
ICPP (2) 1995: 182-185 |
| 16 | | Sissades Tongsima,
Nelson L. Passos,
Edwin Hsing-Mean Sha:
Architecture-Dependent Loop Scheduling via Communication-Sensitive Remapping.
ICPP (2) 1995: 97-104 |
| 15 | EE | Liang-Fang Chao,
Edwin Hsing-Mean Sha:
Static scheduling for synthesis of DSP algorithms on various models.
VLSI Signal Processing 10(3): 207-223 (1995) |
| 1994 |
|---|
| 14 | EE | Nelson L. Passos,
Edwin Hsing-Mean Sha,
Steven C. Bass:
Loop Pipelining for Scheduling Multi-Dimensional Systems via Rotation.
DAC 1994: 485-490 |
| 13 | | Sissades Tongsima,
Nelson L. Passos,
Edwin Hsing-Mean Sha:
Communication Sensitive Rotation Scheduling.
ICCD 1994: 150-153 |
| 12 | | Nelson L. Passos,
Edwin Hsing-Mean Sha:
Full Parallelism in Uniform Nested Loops Using Multi-Dimensional Retiming.
ICPP 1994: 130-133 |
| 11 | | Nelson L. Passos,
Edwin Hsing-Mean Sha,
Steven C. Bass:
Schedule-Based Multi-Dimensional Retiming on Data Flow Graphs.
IPPS 1994: 195-199 |
| 10 | | Nelson L. Passos,
Edwin Hsing-Mean Sha,
Steven C. Bass:
Partitioning and Retiming of Multi-Dimensional Systems.
ISCAS 1994: 227-230 |
| 9 | | Liang-Fang Chao,
Edwin Hsing-Mean Sha:
Retiming and Clock Skew for Synchronous Systems.
ISCAS 1994: 283-286 |
| 1993 |
|---|
| 8 | EE | Liang-Fang Chao,
Andrea S. LaPaugh,
Edwin Hsing-Mean Sha:
Rotation Scheduling: A Loop Pipelining Algorithm.
DAC 1993: 566-572 |
| 7 | | Liang-Fang Chao,
Edwin Hsing-Mean Sha:
Unified Static Scheduling on Various Models.
ICPP 1993: 231-235 |
| 6 | | Liang-Fang Chao,
Edwin Hsing-Mean Sha:
Static Scheduling of Uniform Nested Loops.
IPPS 1993: 254-258 |
| 5 | | Edwin Hsing-Mean Sha,
Kenneth Steiglitz:
Maintaining Bipartite Matchings in the Presence of Failures.
IPPS 1993: 57-64 |
| 4 | | Edwin Hsing-Mean Sha,
Kenneth Steiglitz:
Reconfigurability and Reliability of Systolic/Wavefront Arrays.
IEEE Trans. Computers 42(7): 854-862 (1993) |
| 1992 |
|---|
| 3 | | Liang-Fang Chao,
Edwin Hsing-Mean Sha:
Retiming and Unfolding Data-Flow Graphs.
ICPP (2) 1992: 33-40 |
| 2 | EE | Edwin Hsing-Mean Sha,
Kenneth Steiglitz:
Error detection in arrays via dependency graphs.
VLSI Signal Processing 4(4): 331-342 (1992) |
| 1991 |
|---|
| 1 | | Edwin Hsing-Mean Sha,
Liang-Fang Chao:
Design for Easily Applying Test Vectors to Improve Delay Fault Coverage.
ICCAD 1991: 500-503 |
