2008 |
53 | EE | Yufu Zhang,
Ankur Srivastava,
Mohamed M. Zahran:
Chip level thermal profile estimation using on-chip temperature sensors.
ICCD 2008: 432-437 |
52 | EE | Azadeh Davoodi,
Ankur Srivastava:
Variability Driven Gate Sizing for Binning Yield Optimization.
IEEE Trans. VLSI Syst. 16(6): 683-692 (2008) |
51 | EE | Vishal Khandelwal,
Ankur Srivastava:
Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 610-620 (2008) |
50 | EE | Aswin C. Sankaranarayanan,
Ankur Srivastava,
Rama Chellappa:
Algorithmic and Architectural Optimizations for Computationally Efficient Particle Filtering.
IEEE Transactions on Image Processing 17(5): 737-748 (2008) |
2007 |
49 | EE | Vishal Khandelwal,
Ankur Srivastava:
Monte-Carlo driven stochastic optimization framework for handling fabrication variability.
ICCAD 2007: 105-110 |
48 | EE | Jennifer L. Wong,
Azadeh Davoodi,
Vishal Khandelwal,
Ankur Srivastava,
Miodrag Potkonjak:
Statistical timing analysis using Kernel smoothing.
ICCD 2007: 97-102 |
47 | EE | Vishal Khandelwal,
Ankur Srivastava:
Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation.
ISPD 2007: 11-18 |
46 | EE | Ashish Dobhal,
Vishal Khandelwal,
Ankur Srivastava:
Efficient and Accurate Statistical Timing Analysis for Non-Linear Non-Gaussian Variability With Incremental Attributes.
VLSI Design 2007: 259-264 |
45 | EE | Ashish Dobhal,
Vishal Khandelwal,
Azadeh Davoodi,
Ankur Srivastava:
Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence.
VLSI Design 2007: 571-576 |
44 | EE | Vishal Khandelwal,
Ankur Srivastava:
A Quadratic Modeling-Based Framework for Accurate Statistical Timing Analysis Considering Correlations.
IEEE Trans. VLSI Syst. 15(2): 206-215 (2007) |
43 | EE | Vishal Khandelwal,
Ankur Srivastava:
Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1246-1255 (2007) |
42 | EE | Vishal Khandelwal,
Ankur Srivastava:
Active mode leakage reduction using fine-grained forward body biasing strategy.
Integration 40(4): 561-570 (2007) |
2006 |
41 | EE | Azadeh Davoodi,
Ankur Srivastava:
Variability driven gate sizing for binning yield optimization.
DAC 2006: 959-964 |
40 | EE | Azadeh Davoodi,
Ankur Srivastava:
Probabilistic evaluation of solutions in variability-driven optimization.
ISPD 2006: 17-24 |
39 | EE | Azadeh Davoodi,
Ankur Srivastava:
Effective techniques for the generalized low-power binding problem.
ACM Trans. Design Autom. Electr. Syst. 11(1): 52-69 (2006) |
38 | EE | Azadeh Davoodi,
Vishal Khandelwal,
Ankur Srivastava:
Probabilistic Evaluation of Solutions in Variability-Driven Optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 3010-3016 (2006) |
37 | EE | Jennifer L. Wong,
Azadeh Davoodi,
Vishal Khandelwal,
Ankur Srivastava,
Miodrag Potkonjak:
A statistical methodology for wire-length prediction.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1327-1336 (2006) |
2005 |
36 | EE | Lin Yuan,
Gang Qu,
Ankur Srivastava:
VLSI CAD tool protection by birthmarking design solutions.
ACM Great Lakes Symposium on VLSI 2005: 341-344 |
35 | EE | Azadeh Davoodi,
Ankur Srivastava:
Simultaneous floorplanning and resource binding: a probabilistic approach.
ASP-DAC 2005: 517-522 |
34 | EE | Azadeh Davoodi,
Ankur Srivastava:
Wake-up protocols for controlling current surges in MTCMOS-based technology.
ASP-DAC 2005: 868-871 |
33 | EE | Vishal Khandelwal,
Ankur Srivastava:
A general framework for accurate statistical timing analysis considering correlations.
DAC 2005: 89-94 |
32 | EE | Aswin C. Sankaranarayanan,
Rama Chellappa,
Ankur Srivastava:
Algorithmic and Architectural Design Methodology for Particle Filters in Hardware.
ICCD 2005: 275-280 |
31 | EE | Azadeh Davoodi,
Ankur Srivastava:
Variability-Driven Buffer Insertion Considering Correlations.
ICCD 2005: 425-430 |
30 | EE | Azadeh Davoodi,
Ankur Srivastava:
Probabilistic dual-Vth leakage optimization under variability.
ISLPED 2005: 143-148 |
29 | EE | Azadeh Davoodi,
Ankur Srivastava:
Voltage scheduling under unpredictabilities: a risk management paradigm.
ACM Trans. Design Autom. Electr. Syst. 10(2): 354-368 (2005) |
28 | EE | Vishal Khandelwal,
Azadeh Davoodi,
Ankur Srivastava:
Simultaneous V/sub t/ selection and assignment for leakage optimization.
IEEE Trans. VLSI Syst. 13(6): 762-765 (2005) |
27 | EE | Azadeh Davoodi,
Ankur Srivastava:
Power-driven simultaneous resource binding and floorplanning: a probabilistic approach.
IEEE Trans. VLSI Syst. 13(8): 934-942 (2005) |
26 | EE | Ankur Srivastava,
Seda Ogrenci Memik,
Bo-Kyung Choi,
Majid Sarrafzadeh:
On effective slack management in postscheduling phase.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 645-653 (2005) |
2004 |
25 | EE | Azadeh Davoodi,
Vishal Khandelwal,
Ankur Srivastava:
High level techniques for power-grid noise immunity.
ACM Great Lakes Symposium on VLSI 2004: 13-18 |
24 | EE | Azadeh Davoodi,
Vishal Khandelwal,
Ankur Srivastava:
Variability inspired implementation selection problem.
ICCAD 2004: 423-427 |
23 | EE | Vishal Khandelwal,
Azadeh Davoodi,
Ankur Srivastava:
Efficient statistical timing analysis through error budgeting.
ICCAD 2004: 473-477 |
22 | EE | Vishal Khandelwal,
Ankur Srivastava:
Leakage control through fine-grained placement and sizing of sleep transistors.
ICCAD 2004: 533-536 |
21 | EE | Jennifer L. Wong,
Azadeh Davoodi,
Vishal Khandelwal,
Ankur Srivastava,
Miodrag Potkonjak:
Wire-length prediction using statistical techniques.
ICCAD 2004: 702-705 |
20 | EE | Vishal Khandelwal,
Ankur Srivastava:
Active mode leakage reduction using fine-grained forward body biasing strategy.
ISLPED 2004: 150-155 |
19 | | Ankur Srivastava,
Ryan Kastner,
Chunhong Chen,
Majid Sarrafzadeh:
Timing driven gate duplication.
IEEE Trans. VLSI Syst. 12(1): 42-51 (2004) |
18 | EE | Azadeh Davoodi,
Vishal Khandelwal,
Ankur Srivastava:
Empirical models for net-length probability distribution and applications.
IEEE Trans. VLSI Syst. 12(10): 1066-1075 (2004) |
2003 |
17 | EE | Ankur Srivastava,
Seda Ogrenci Memik,
Bo-Kyung Choi,
Majid Sarrafzadeh:
Achieving Design Closure Through Delay Relaxation Parameter.
ICCAD 2003: 54-57 |
16 | EE | Vishal Khandelwal,
Azadeh Davoodi,
Akash Nanavati,
Ankur Srivastava:
A Probabilistic Approach to Buffer Insertion.
ICCAD 2003: 560-567 |
15 | EE | Ankur Srivastava:
Simultaneous Vt selection and assignment for leakage optimization.
ISLPED 2003: 146-151 |
14 | EE | Azadeh Davoodi,
Ankur Srivastava:
Effective graph theoretic techniques for the generalized low power binding problem.
ISLPED 2003: 152-157 |
13 | EE | Azadeh Davoodi,
Ankur Srivastava:
Voltage scheduling under unpredictabilities: a risk management paradigm.
ISLPED 2003: 302-305 |
2002 |
12 | EE | Ankur Srivastava,
Majid Sarrafzadeh:
Predictability: definition, ananlysis and optimization.
ICCAD 2002: 118-121 |
11 | EE | Eren Kursun,
Ankur Srivastava,
Seda Ogrenci Memik,
Majid Sarrafzadeh:
Early evaluation techniques for low power binding.
ISLPED 2002: 160-165 |
10 | | Ankur Srivastava,
Majid Sarrafzadeh:
Predictability: Definition, Analysis and Optimization.
IWLS 2002: 267-272 |
9 | EE | Chunhong Chen,
Elaheh Bozorgzadeh,
Ankur Srivastava,
Majid Sarrafzadeh:
Budget Management with Applications.
Algorithmica 34(3): 261-275 (2002) |
8 | EE | Ankur Srivastava,
Eren Kursun,
Majid Sarrafzadeh:
Predictability in RT-Level Designs.
Journal of Circuits, Systems, and Computers 11(4): 323-332 (2002) |
2001 |
7 | EE | Abhishek Ranjan,
Ankur Srivastava,
V. Karnam,
Majid Sarrafzadeh:
Layout aware retiming.
ACM Great Lakes Symposium on VLSI 2001: 25-30 |
6 | EE | Ankur Srivastava,
Chunhong Chen,
Majid Sarrafzadeh:
Timing driven gate duplication in technology independent phase.
ASP-DAC 2001: 577-582 |
5 | EE | Majid Sarrafzadeh,
Elaheh Bozorgzadeh,
Ryan Kastner,
Ankur Srivastava:
Design and analysis of physical design algorithms.
ISPD 2001: 82-89 |
4 | EE | Chunhong Chen,
Ankur Srivastava,
Majid Sarrafzadeh:
On gate level power optimization using dual-supply voltages.
IEEE Trans. VLSI Syst. 9(5): 616-629 (2001) |
3 | EE | Amir H. Farrahi,
Chunhong Chen,
Ankur Srivastava,
Gustavo E. Téllez,
Majid Sarrafzadeh:
Activity-driven clock design.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 705-714 (2001) |
2 | EE | Ankur Srivastava,
Ryan Kastner,
Majid Sarrafzadeh:
On the complexity of gate duplication.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1170-1176 (2001) |
2000 |
1 | | Ankur Srivastava,
Ryan Kastner,
Majid Sarrafzadeh:
Timing Driven Gate Duplication: Complexity Issues and Algorithms.
ICCAD 2000: 447-450 |