| 2008 |
|---|
| 93 | EE | Khaled R. Heloue,
Farid N. Najm:
Parameterized timing analysis with general delay models and arbitrary variation sources.
DAC 2008: 403-408 |
| 92 | EE | Khaled R. Heloue,
Sari Onaissi,
Farid N. Najm:
Efficient block-based parameterized timing analysis covering all potentially critical paths.
ICCAD 2008: 173-180 |
| 91 | EE | Khaled R. Heloue,
Farid N. Najm:
Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1826-1839 (2008) |
| 90 | EE | Sari Onaissi,
Farid N. Najm:
A Linear-Time Approach for Static Timing Analysis Covering All Process Corners.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1291-1304 (2008) |
| 2007 |
|---|
| 89 | EE | Khaled R. Heloue,
Navid Azizi,
Farid N. Najm:
Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation.
DAC 2007: 93-98 |
| 88 | EE | Hratch Mangassarian,
Andreas G. Veneris,
Sean Safarpour,
Farid N. Najm,
Magdy S. Abadir:
Maximum circuit activity estimation using pseudo-boolean satisfiability.
DATE 2007: 1538-1543 |
| 87 | EE | Imad A. Ferzli,
Farid N. Najm,
Lars Kruse:
A geometric approach for early power grid verification using current constraints.
ICCAD 2007: 40-47 |
| 86 | EE | Imad A. Ferzli,
Farid N. Najm,
Lars Kruse:
Early power grid verification under circuit current uncertainties.
ISLPED 2007: 116-121 |
| 85 | EE | Navid Azizi,
Muhammad M. Khellah,
Vivek De,
Farid N. Najm:
Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling.
IEEE Trans. VLSI Syst. 15(7): 746-757 (2007) |
| 84 | EE | Farid N. Najm,
Noel Menezes,
Imad A. Ferzli:
A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 574-591 (2007) |
| 2006 |
|---|
| 83 | EE | Georges Nabaa,
Navid Azizi,
Farid N. Najm:
An adaptive FPGA architecture with process variation compensation and reduced leakage.
DAC 2006: 624-629 |
| 82 | EE | Navid Azizi,
Farid N. Najm:
A family of cells to reduce the soft-error-rate in ternary-CAM.
DAC 2006: 779-784 |
| 81 | EE | Nahi H. Abdul Ghani,
Farid N. Najm:
Handling inductance in early power grid verification.
ICCAD 2006: 127-134 |
| 80 | EE | Sari Onaissi,
Farid N. Najm:
A linear-time approach for static timing analysis covering all process corners.
ICCAD 2006: 217-224 |
| 79 | EE | Imad A. Ferzli,
Farid N. Najm:
Analysis and verification of power grids considering process-induced leakage-current variations.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 126-143 (2006) |
| 78 | EE | Dionysios Kouroussis,
Rubil Ahmadi,
Farid N. Najm:
Voltage-Aware Static Timing Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2156-2169 (2006) |
| 77 | EE | Jason Helge Anderson,
Farid N. Najm:
Active leakage power optimization for FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 423-437 (2006) |
| 76 | EE | Srinivas Bodapati,
Farid N. Najm:
High-level current macro model for logic blocks.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 837-855 (2006) |
| 75 | EE | Bin Wu,
Jianwen Zhu,
Farid N. Najm:
Dynamic-range estimation.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1618-1636 (2006) |
| 2005 |
|---|
| 74 | EE | David Blaauw,
Anirudh Devgan,
Farid N. Najm:
Leakage power: trends, analysis and avoidance.
ASP-DAC 2005 |
| 73 | EE | Navid Azizi,
Muhammad M. Khellah,
Vivek De,
Farid N. Najm:
Variations-aware low-power design with voltage scaling.
DAC 2005: 529-534 |
| 72 | EE | Farid N. Najm:
On the need for statistical timing analysis.
DAC 2005: 764-765 |
| 71 | EE | Bin Wu,
Jianwen Zhu,
Farid N. Najm:
A non-parametric approach for dynamic range estimation of nonlinear systems.
DAC 2005: 841-844 |
| 70 | | Dionysios Kouroussis,
Imad A. Ferzli,
Farid N. Najm:
Incremental partitioning-based vectorless power grid verification.
ICCAD 2005: 358-364 |
| 69 | | Khaled R. Heloue,
Farid N. Najm:
Statistical timing analysis with two-sided constraints.
ICCAD 2005: 829-836 |
| 68 | EE | Maha Nizam,
Farid N. Najm,
Anirudh Devgan:
Power grid voltage integrity verification.
ISLPED 2005: 239-244 |
| 67 | EE | Andreas Moshovos,
Babak Falsafi,
Farid N. Najm,
Navid Azizi:
A Case for Asymmetric-Cell Cache Memories.
IEEE Trans. VLSI Syst. 13(7): 877-881 (2005) |
| 66 | EE | Kavel M. Büyüksahin,
Farid N. Najm:
Early power estimation for VLSI circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1076-1088 (2005) |
| 2004 |
|---|
| 65 | EE | Jason Helge Anderson,
Farid N. Najm:
Interconnect capacitance estimation for FPGAs.
ASP-DAC 2004: 713-718 |
| 64 | EE | Farid N. Najm,
Noel Menezes:
Statistical timing analysis based on a timing yield model.
DAC 2004: 460-465 |
| 63 | EE | Bin Wu,
Jianwen Zhu,
Farid N. Najm:
An analytical approach for dynamic range estimation.
DAC 2004: 472-477 |
| 62 | EE | Dionysios Kouroussis,
Rubil Ahmadi,
Farid N. Najm:
Worst-case circuit delay taking into account power supply variations.
DAC 2004: 652-657 |
| 61 | EE | Jason Helge Anderson,
Farid N. Najm,
Tim Tuan:
Active leakage power optimization for FPGAs.
FPGA 2004: 33-41 |
| 60 | EE | Jason Helge Anderson,
Farid N. Najm:
Low-power programmable routing circuitry for FPGAs.
ICCAD 2004: 602-609 |
| 59 | EE | Bin Wu,
Jianwen Zhu,
Farid N. Najm:
Dynamic range estimation for nonlinear systems.
ICCAD 2004: 660-667 |
| 58 | EE | Navid Azizi,
Farid N. Najm:
An Asymmetric SRAM Cell to Lower Gate Leakage.
ISQED 2004: 534-539 |
| 57 | EE | Jason Helge Anderson,
Farid N. Najm:
Power estimation techniques for FPGAs.
IEEE Trans. VLSI Syst. 12(10): 1015-1027 (2004) |
| 2003 |
|---|
| 56 | EE | Imad A. Ferzli,
Farid N. Najm:
Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations.
DAC 2003: 856-859 |
| 55 | EE | Dionysios Kouroussis,
Farid N. Najm:
A static pattern-independent technique for power grid voltage integrity verification.
DAC 2003: 99-104 |
| 54 | EE | Rubil Ahmadi,
Farid N. Najm:
Timing Analysis in Presence of Power Supply and Ground Voltage Variations.
ICCAD 2003: 176-183 |
| 53 | EE | Imad A. Ferzli,
Farid N. Najm:
Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations.
ICCAD 2003: 770-777 |
| 52 | EE | Kavel M. Büyüksahin,
Priyadarsan Patra,
Farid N. Najm:
ESTIMA: an architectural-level power estimator for multi-ported pipelined register files.
ISLPED 2003: 294-297 |
| 51 | EE | Rafik S. Guindi,
Farid N. Najm:
Design Techniques for Gate-Leakage Reduction in CMOS Circuits.
ISQED 2003: 61- |
| 50 | EE | Jason Helge Anderson,
Farid N. Najm:
Switching activity analysis and pre-layout activity prediction for FPGAs.
SLIP 2003: 15-21 |
| 49 | EE | Subodh Gupta,
Farid N. Najm:
Energy and peak-current per-cycle estimation at RTL.
IEEE Trans. VLSI Syst. 11(4): 525-537 (2003) |
| 48 | EE | Navid Azizi,
Farid N. Najm,
Andreas Moshovos:
Low-leakage asymmetric-cell SRAM.
IEEE Trans. VLSI Syst. 11(4): 701-715 (2003) |
| 2002 |
|---|
| 47 | EE | Srinivas Bodapati,
Farid N. Najm:
High-level current macro-model for power-grid analysis.
DAC 2002: 385-390 |
| 46 | EE | Kavel M. Büyüksahin,
Farid N. Najm:
High-level area estimation.
ISLPED 2002: 271-274 |
| 45 | EE | Navid Azizi,
Andreas Moshovos,
Farid N. Najm:
Low-leakage asymmetric-cell SRAM.
ISLPED 2002: 48-51 |
| 44 | EE | Vikram Saxena,
Farid N. Najm,
Ibrahim N. Hajj:
Estimation of state line statistics in sequential circuits.
ACM Trans. Design Autom. Electr. Syst. 7(3): 455-473 (2002) |
| 43 | EE | Sumant Ramprasad,
Ibrahim N. Hajj,
Farid N. Najm:
A technique for Improving dual-output domino logic.
IEEE Trans. VLSI Syst. 10(4): 508-511 (2002) |
| 42 | EE | Joseph N. Kozhaya,
Sani R. Nassif,
Farid N. Najm:
A multigrid-like technique for power grid analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1148-1160 (2002) |
| 2001 |
|---|
| 41 | EE | Joseph N. Kozhaya,
Sani R. Nassif,
Farid N. Najm:
Multigrid-Like Technique for Power Grid Analysis.
ICCAD 2001: 480-487 |
| 40 | EE | Srinivas Bodapati,
Farid N. Najm:
Frequency-domain supply current macro-model.
ISLPED 2001: 295-298 |
| 39 | EE | Joseph N. Kozhaya,
Farid N. Najm:
Power estimation for large sequential circuits.
IEEE Trans. VLSI Syst. 9(2): 400-407 (2001) |
| 2000 |
|---|
| 38 | EE | Kavel M. Büyüksahin,
Farid N. Najm:
High-level power estimation with interconnect effects.
ISLPED 2000: 197-202 |
| 37 | EE | Gilbert Yoh,
Farid N. Najm:
A Statistical Model for Electromigration Failures.
ISQED 2000: 45-50 |
| 36 | EE | Srinivas Bodapati,
Farid N. Najm:
Pre-layout estimation of individual wire lengths.
SLIP 2000: 93-98 |
| 35 | EE | Subodh Gupta,
Farid N. Najm:
Power modeling for high-level power estimation.
IEEE Trans. VLSI Syst. 8(1): 18-29 (2000) |
| 34 | EE | Subodh Gupta,
Farid N. Najm:
Analytical models for RTL power estimation of combinational andsequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(7): 808-814 (2000) |
| 1999 |
|---|
| 33 | | Farid N. Najm,
Jason Cong,
David Blaauw:
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, San Diego, California, USA, August 16-17, 1999
ACM 1999 |
| 32 | EE | Subodh Gupta,
Farid N. Najm:
Power macro-models for DSP blocks with application to high-level synthesis.
ISLPED 1999: 103-105 |
| 31 | EE | Subodh Gupta,
Farid N. Najm:
Energy-per-cycle estimation at RTL.
ISLPED 1999: 121-126 |
| 30 | EE | Sumant Ramprasad,
Ibrahim N. Hajj,
Farid N. Najm:
An optimization technique for dual-output domino logic.
ISLPED 1999: 258-260 |
| 29 | EE | Mahadevamurty Nemani,
Farid N. Najm:
High-level area and power estimation for VLSI circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 697-713 (1999) |
| 1998 |
|---|
| 28 | EE | Mahadevamurty Nemani,
Farid N. Najm:
Delay Estimation VLSI Circuits from a High-Level View.
DAC 1998: 591-594 |
| 1997 |
|---|
| 27 | EE | Subodh Gupta,
Farid N. Najm:
Power Macromodeling for High Level Power Estimation.
DAC 1997: 365-370 |
| 26 | EE | Rajendran Panda,
Farid N. Najm:
Technology-Dependent Transformations for Low-Power Synthesis.
DAC 1997: 650-655 |
| 25 | EE | Vikram Saxena,
Farid N. Najm,
Ibrahim N. Hajj:
Monte-Carlo approach for power estimation in sequential circuits.
ED&TC 1997: 416-420 |
| 24 | EE | Mahadevamurty Nemani,
Farid N. Najm:
High-level area and power estimation for VLSI circuits.
ICCAD 1997: 114-119 |
| 23 | EE | Joseph N. Kozhaya,
Farid N. Najm:
Accurate power estimation for large sequential circuits.
ICCAD 1997: 488-493 |
| 1996 |
|---|
| 22 | EE | Mahadevamurty Nemani,
Farid N. Najm:
High-level power estimation and the area complexity of Boolean functions.
ISLPED 1996: 329-334 |
| 21 | EE | Mahadevamurty Nemani,
Farid N. Najm:
Towards a high-level power estimation capability [digital ICs].
IEEE Trans. on CAD of Integrated Circuits and Systems 15(6): 588-598 (1996) |
| 1995 |
|---|
| 20 | EE | Farid N. Najm:
Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits.
DAC 1995: 612-617 |
| 19 | EE | Farid N. Najm,
Michael Y. Zhang:
Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuits.
DAC 1995: 623-627 |
| 18 | EE | Farid N. Najm,
Shashank Goel,
Ibrahim N. Hajj:
Power Estimation in Sequential Circuits.
DAC 1995: 635-640 |
| 17 | EE | Farid N. Najm:
Power estimation techniques for integrated circuits.
ICCAD 1995: 492-499 |
| 16 | EE | Farid N. Najm:
Towards a high-level power estimation capability.
ISLPD 1995: 87-92 |
| 15 | EE | Harish Kriplani,
Farid N. Najm,
Ibrahim N. Hajj:
Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(8): 998-1012 (1995) |
| 1994 |
|---|
| 14 | EE | Michael G. Xakellis,
Farid N. Najm:
Statistical Estimation of the Switching Activity in Digital Circuits.
DAC 1994: 728-733 |
| 13 | | Harish Kriplani,
Farid N. Najm,
Ibrahim N. Hajj:
Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits.
ISCAS 1994: 435-438 |
| 12 | EE | Farid N. Najm:
A survey of power estimation techniques in VLSI circuits.
IEEE Trans. VLSI Syst. 2(4): 446-455 (1994) |
| 11 | EE | Farid N. Najm:
Low-pass filter for computing the transition density in digital circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(9): 1123-1131 (1994) |
| 1993 |
|---|
| 10 | EE | Harish Kriplani,
Farid N. Najm,
Ping Yang,
Ibrahim N. Hajj:
Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits.
DAC 1993: 384-388 |
| 9 | EE | Richard Burch,
Farid N. Najm,
Ping Yang,
Timothy N. Trick:
A Monte Carlo approach for power estimation.
IEEE Trans. VLSI Syst. 1(1): 63-71 (1993) |
| 8 | EE | Farid N. Najm:
Transition density: a new measure of activity in digital circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(2): 310-323 (1993) |
| 1992 |
|---|
| 7 | EE | Harish Kriplani,
Farid N. Najm,
Ibrahim N. Hajj:
Maximum Current Estimation in CMOS Circuits.
DAC 1992: 2-7 |
| 6 | EE | Richard Burch,
Farid N. Najm,
Ping Yang,
Timothy N. Trick:
McPOWER: a Monte Carlo approach to power estimation.
ICCAD 1992: 90-97 |
| 1991 |
|---|
| 5 | EE | Farid N. Najm:
Transition Density, A Stochastic Measure of Activity in Digital Circuits.
DAC 1991: 644-649 |
| 4 | EE | Farid N. Najm,
Ibrahim N. Hajj,
Ping Yang:
An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(11): 1372-1381 (1991) |
| 1990 |
|---|
| 3 | EE | Farid N. Najm,
Richard Burch,
Ping Yang,
Ibrahim N. Hajj:
Probabilistic simulation for reliability analysis of CMOS VLSI circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(4): 439-450 (1990) |
| 2 | EE | Farid N. Najm,
Ibrahim N. Hajj:
The complexity of fault detection in MOS VLSI circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(9): 995-1001 (1990) |
| 1988 |
|---|
| 1 | EE | Richard Burch,
Farid N. Najm,
Ping Yang,
Dale E. Hocevar:
Pattern-Independent Current Estimation for Reliability Analysis of CMOS Circuits.
DAC 1988: 294-299 |
