| 2009 |
|---|
| 72 | EE | Alessandro Cevrero,
Panagiotis Athanasopoulos,
Hadi Parandeh-Afshar,
Philip Brisk,
Yusuf Leblebici,
Paolo Ienne,
Maurizio Skerlj:
3D configuration caching for 2D FPGAs.
FPGA 2009: 286 |
| 71 | EE | Theo Kluter,
Philip Brisk,
Edoardo Charbon,
Paolo Ienne:
MPSoC Design Using Application-Specific Architecturally Visible Communication.
HiPEAC 2009: 183-197 |
| 70 | EE | Francesco Regazzoni,
Thomas Eisenbarth,
Axel Poschmann,
Johann Großschädl,
Frank K. Gürkaynak,
Marco Macchetti,
Zeynep Toprak Deniz,
Laura Pozzi,
Christof Paar,
Yusuf Leblebici,
Paolo Ienne:
Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology.
Transactions on Computational Science 4: 230-243 (2009) |
| 2008 |
|---|
| 69 | EE | Hadi Parandeh-Afshar,
Philip Brisk,
Paolo Ienne:
Efficient synthesis of compressor trees on FPGAs.
ASP-DAC 2008: 138-143 |
| 68 | EE | Ajay K. Verma,
Philip Brisk,
Paolo Ienne:
Fast, quasi-optimal, and pipelined instruction-set extensions.
ASP-DAC 2008: 334-339 |
| 67 | EE | Seyed Hosein Attarzadeh Niaki,
Alessandro Cevrero,
Philip Brisk,
Chrysostomos Nicopoulos,
Frank K. Gürkaynak,
Yusuf Leblebici,
Paolo Ienne:
Design space exploration for field programmable compressor trees.
CASES 2008: 207-216 |
| 66 | EE | Theo Kluter,
Philip Brisk,
Paolo Ienne,
Edoardo Charbon:
Speculative DMA for architecturally visible storage in instruction set extensions.
CODES+ISSS 2008: 243-248 |
| 65 | EE | Ajay K. Verma,
Philip Brisk,
Paolo Ienne:
Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design.
DATE 2008: 1250-1255 |
| 64 | EE | Hadi Parandeh-Afshar,
Philip Brisk,
Paolo Ienne:
Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming.
DATE 2008: 1256-1261 |
| 63 | EE | Francesco Regazzoni,
Thomas Eisenbarth,
Luca Breveglieri,
Paolo Ienne,
Israel Koren:
Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?.
DFT 2008: 202-210 |
| 62 | EE | Hadi Parandeh-Afshar,
Philip Brisk,
Paolo Ienne:
A novel FPGA logic block for improved arithmetic performance.
FPGA 2008: 171-180 |
| 61 | EE | Alessandro Cevrero,
Panagiotis Athanasopoulos,
Hadi Parandeh-Afshar,
Ajay K. Verma,
Philip Brisk,
Frank K. Gürkaynak,
Yusuf Leblebici,
Paolo Ienne:
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs.
FPGA 2008: 181-190 |
| 60 | EE | Maurizio Skerlj,
Paolo Ienne:
Error Protected Data Bus Inversion Using Standard DRAM Components.
ISQED 2008: 35-42 |
| 59 | EE | Paolo Ienne,
P. Petrov:
Guest Editorial Special Section on Application Specific Processors.
IEEE Trans. VLSI Syst. 16(10): 1257-1258 (2008) |
| 58 | EE | Ajay K. Verma,
Philip Brisk,
Paolo Ienne:
Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1761-1774 (2008) |
| 2007 |
|---|
| 57 | EE | Ajay K. Verma,
Paolo Ienne:
Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands.
ASP-DAC 2007: 601-608 |
| 56 | EE | Ajay K. Verma,
Philip Brisk,
Paolo Ienne:
Rethinking custom ISE identification: a new processor-agnostic method.
CASES 2007: 125-134 |
| 55 | EE | Philip Brisk,
Ajay K. Verma,
Paolo Ienne:
An optimistic and conservative register assignment heuristic for chordal graphs.
CASES 2007: 209-217 |
| 54 | EE | Philip Brisk,
Ajay K. Verma,
Paolo Ienne,
Hadi Parandeh-Afshar:
Enhancing FPGA Performance for Arithmetic Circuits.
DAC 2007: 334-337 |
| 53 | EE | Ajay K. Verma,
Philip Brisk,
Paolo Ienne:
Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits.
DAC 2007: 404-409 |
| 52 | EE | Ajay K. Verma,
Paolo Ienne:
Automatic synthesis of compressor trees: reevaluating large counters.
DATE 2007: 443-448 |
| 51 | EE | Francesco Regazzoni,
Thomas Eisenbarth,
Johann Großschädl,
Luca Breveglieri,
Paolo Ienne,
Israel Koren,
Christof Paar:
Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits.
DFT 2007: 508-516 |
| 50 | EE | Philip Brisk,
Ajay K. Verma,
Paolo Ienne:
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design.
ICCAD 2007: 172-179 |
| 49 | EE | Francesco Regazzoni,
Stéphane Badel,
Thomas Eisenbarth,
Johann Großschädl,
Axel Poschmann,
Zeynep Toprak Deniz,
Marco Macchetti,
Laura Pozzi,
Christof Paar,
Yusuf Leblebici,
Paolo Ienne:
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies.
ICSAMOS 2007: 209-214 |
| 48 | EE | Frederic Worm,
Patrick Thiran,
Paolo Ienne:
Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating Designs.
ISQED 2007: 861-866 |
| 47 | EE | Partha Biswas,
Sudarshan Banerjee,
Nikil Dutt,
Laura Pozzi,
Paolo Ienne:
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
CoRR abs/0710.4820: (2007) |
| 46 | EE | Partha Biswas,
Nikil D. Dutt,
Laura Pozzi,
Paolo Ienne:
Introduction of Architecturally Visible Storage in Instruction Set Extensions.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 435-446 (2007) |
| 2006 |
|---|
| 45 | EE | Ajay K. Verma,
Paolo Ienne:
Towards the automatic exploration of arithmetic-circuit architectures.
DAC 2006: 445-450 |
| 44 | EE | Partha Biswas,
Nikil D. Dutt,
Paolo Ienne,
Laura Pozzi:
Automatic identification of application-specific functional units with architecturally visible storage.
DATE 2006: 212-217 |
| 43 | EE | Johann Großschädl,
Paolo Ienne,
Laura Pozzi,
Stefan Tillich,
Ajay K. Verma:
Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography.
DATE 2006: 218-223 |
| 42 | EE | Frederic Worm,
Patrick Thiran,
Paolo Ienne:
Designing Robust Checkers in the Presence of Massive Timing Errors.
IOLTS 2006: 281-286 |
| 41 | EE | Partha Biswas,
Sudarshan Banerjee,
Nikil D. Dutt,
Paolo Ienne,
Laura Pozzi:
Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core.
VLSI Design 2006: 651-656 |
| 40 | EE | Derin Derin Harmanci,
Nuria Pazos,
Paolo Ienne,
Yusuf Leblebici:
A Predictable Communication Scheme for Embedded Multiprocessor Systems.
VLSI-SoC 2006: 152-157 |
| 39 | EE | Partha Biswas,
Sudarshan Banerjee,
Nikil D. Dutt,
Laura Pozzi,
Paolo Ienne:
ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processors.
IEEE Trans. VLSI Syst. 14(7): 754-762 (2006) |
| 38 | EE | Miljan Vuletic,
Laura Pozzi,
Paolo Ienne:
Virtual memory window for application-specific reconfigurable coprocessors.
IEEE Trans. VLSI Syst. 14(8): 910-915 (2006) |
| 37 | EE | Laura Pozzi,
Kubilay Atasu,
Paolo Ienne:
Exact and approximate algorithms for the extension of embedded processor instruction sets.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1209-1229 (2006) |
| 2005 |
|---|
| 36 | EE | Frederic Worm,
Patrick Thiran,
Paolo Ienne:
A Unified Coding Framework for Delay-Insensitivity.
ASYNC 2005: 201-211 |
| 35 | EE | Laura Pozzi,
Paolo Ienne:
Exploiting pipelining to relax register-file port constraints of instruction-set extensions.
CASES 2005: 2-10 |
| 34 | EE | Miljan Vuletic,
Christophe Dubach,
Laura Pozzi,
Paolo Ienne:
Enabling unrestricted automated synthesis of portable hardware accelerators for virtual machines.
CODES+ISSS 2005: 243-248 |
| 33 | EE | Partha Biswas,
Sudarshan Banerjee,
Nikil D. Dutt,
Laura Pozzi,
Paolo Ienne:
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement.
DATE 2005: 1246-1251 |
| 32 | EE | Soner Yaldiz,
Alper Demir,
Serdar Tasiran,
Paolo Ienne,
Yusuf Leblebici:
Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems.
ESTImedia 2005: 135-140 |
| 31 | EE | Mehmet Derin Harmanci,
Nuria Pazos Escudero,
Yusuf Leblebici,
Paolo Ienne:
Quantitative modelling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip.
ISCAS (2) 2005: 1782-1785 |
| 30 | EE | Frederic Worm,
Paolo Ienne,
Patrick Thiran,
Giovanni De Micheli:
Self-calibrating networks-on-chip.
ISCAS (3) 2005: 2361-2364 |
| 29 | EE | Miljan Vuletic,
Laura Pozzi,
Paolo Ienne:
Seamless Hardware-Software Integration in Reconfigurable Computing Systems.
IEEE Design & Test of Computers 22(2): 102-113 (2005) |
| 28 | EE | Frederic Worm,
Paolo Ienne,
Patrick Thiran,
Giovanni De Micheli:
A robust self-calibrating transmission scheme for on-chip networks.
IEEE Trans. VLSI Syst. 13(1): 126-139 (2005) |
| 2004 |
|---|
| 27 | EE | Miljan Vuletic,
Laura Pozzi,
Paolo Ienne:
Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing.
ASAP 2004: 339-351 |
| 26 | EE | Marc Epalza,
Paolo Ienne,
Daniel Mlynek:
Dynamic Reallocation of Functional Units in Superscalar Processors.
Asia-Pacific Computer Systems Architecture Conference 2004: 185-198 |
| 25 | EE | Partha Biswas,
Vinay Choudhary,
Kubilay Atasu,
Laura Pozzi,
Paolo Ienne,
Nikil Dutt:
Introduction of local memory elements in instruction set extensions.
DAC 2004: 729-734 |
| 24 | EE | Miljan Vuletic,
Laura Pozzi,
Paolo Ienne:
Virtual memory window for application-specific reconfigurable coprocessors.
DAC 2004: 948-953 |
| 23 | EE | Miljan Vuletic,
Ludovic Righetti,
Laura Pozzi,
Paolo Ienne:
Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors.
DATE 2004: 748 |
| 22 | EE | Paolo Ienne,
Ajay K. Verma:
Arithmetic Transformations to Maximise the Use of Compressor Trees.
DELTA 2004: 219-224 |
| 21 | EE | Miljan Vuletic,
Laura Pozzi,
Paolo Ienne:
Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor.
FCCM 2004: 24-33 |
| 20 | EE | Miljan Vuletic,
Laura Pozzi,
Paolo Ienne:
Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors.
FPL 2004: 596-605 |
| 19 | EE | Frederic Worm,
Paolo Ienne,
Patrick Thiran:
Soft self-synchronising codes for self-calibrating communication.
ICCAD 2004: 440-447 |
| 18 | EE | Ajay K. Verma,
Paolo Ienne:
Improved use of the carry-save representation for the synthesis of complex arithmetic circuits.
ICCAD 2004: 791-798 |
| 17 | EE | Marc Epalza,
Paolo Ienne,
Daniel Mlynek:
Adding Limited Reconfigurability to Superscalar Processors.
IEEE PACT 2004: 53-62 |
| 16 | EE | Diviya Jain,
Anshul Kumar,
Laura Pozzi,
Paolo Ienne:
Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units.
SCOPES 2004: 17-32 |
| 15 | EE | Frederic Worm,
Paolo Ienne,
Patrick Thiran,
Giovanni De Micheli:
On-Chip Self-Calibrating Communication Techniques Robust to Electrical Parameter Variations.
IEEE Design & Test of Computers 21(6): 524-535 (2004) |
| 2003 |
|---|
| 14 | EE | Armita Peymandoust,
Laura Pozzi,
Paolo Ienne,
Giovanni De Micheli:
Automatic Instruction Set Extension and Utilization for Embedded Processors.
ASAP 2003: 108- |
| 13 | EE | Kubilay Atasu,
Laura Pozzi,
Paolo Ienne:
Automatic application-specific instruction-set extensions under microarchitectural constraints.
DAC 2003: 256-261 |
| 12 | EE | Kubilay Atasu,
Laura Pozzi,
Paolo Ienne:
Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints.
International Journal of Parallel Programming 31(6): 411-428 (2003) |
| 2002 |
|---|
| 11 | EE | Laura Pozzi,
Miljan Vuletic,
Paolo Ienne:
Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors.
DATE 2002: 1138 |
| 10 | EE | M. Balakrishnan,
Anshul Kumar,
Paolo Ienne,
Anup Gangwar,
Bhuvan Middha:
A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units.
ISSS 2002: 2-7 |
| 9 | EE | Paolo Ienne,
Patrick Thiran,
Giovanni De Micheli,
Frederic Worm:
An Adaptive Low-Power Transmission Scheme for On-Chip Networks.
ISSS 2002: 92-100 |
| 1998 |
|---|
| 8 | EE | Paolo Ienne,
Alexander Grießing:
Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts?
DAC 1998: 396-401 |
| 1997 |
|---|
| 7 | | Paolo Ienne:
Digital Connectionist Hardware: Current Problems and Future Challenges.
IWANN 1997: 688-713 |
| 1996 |
|---|
| 6 | EE | Thierry Cornu,
Paolo Ienne,
Dagmar Niebur,
Patrick Thiran,
Marc A. Viredaz:
Design, Implementation, and Test of a Multi-Model Systolic Neural-Network Accelerator.
Scientific Programming 5(1): 47-61 (1996) |
| 5 | EE | Paolo Ienne,
Thierry Cornu,
Gary Kuhn:
Special-purpose digital hardware for neural networks: An architectural survey.
VLSI Signal Processing 13(1): 5-25 (1996) |
| 1995 |
|---|
| 4 | EE | Paolo Ienne:
Horizontal Microcode Compaction for Programmable Systolic Accelerators.
ASAP 1995: 85- |
| 3 | EE | Paolo Ienne,
Marc A. Viredaz:
GENES IV: A bit-serial processing element for a multi-model neural-network accelerator.
VLSI Signal Processing 9(3): 257-273 (1995) |
| 1994 |
|---|
| 2 | | Paolo Ienne,
Marc A. Viredaz:
Bit-Serial Multipliers and Squarers.
IEEE Trans. Computers 43(12): 1445-1450 (1994) |
| 1993 |
|---|
| 1 | | Francesco Mondada,
Edoardo Franzi,
Paolo Ienne:
Mobile Robot Miniaturisation: A Tool for Investigation in Control Algorithms.
ISER 1993: 501-513 |
