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Debjit Sinha

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2008
18EEPeter Feldmann, Soroush Abbaspour, Debjit Sinha, Gregory Schaeffer, Revanta Banerji, Hemlata Gupta: Driver waveform computation for timing analysis with multiple voltage threshold driver models. DAC 2008: 425-428
17EEDebjit Sinha, Gregory Schaeffer, Soroush Abbaspour, Alex Rubin, Frank Borkam: Constrained aggressor set selection for maximum coupling noise. ICCAD 2008: 790-796
2007
16EEDebjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou: Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. VLSI Design 2007: 875-880
15EEArindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou: Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 447-455 (2007)
14EEDebjit Sinha, Hai Zhou, Narendra V. Shenoy: Advances in Computation of the Maximum of a Set of Gaussian Random Variables. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1522-1533 (2007)
2006
13EEArindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou: Smart bit-width allocation for low power optimization in a systemc based ASIC design environment. DATE 2006: 618-623
12EEDebjit Sinha, DiaaEldin Khalil, Yehea I. Ismail, Hai Zhou: A timing dependent power estimation framework considering coupling. ICCAD 2006: 401-407
11EEDebjit Sinha, Hai Zhou, Narendra V. Shenoy: Advances in Computation of the Maximum of a Set of Random Variables. ISQED 2006: 306-311
10EESerkan Ozdemir, Debjit Sinha, Gokhan Memik, Jonathan Adams, Hai Zhou: Yield-Aware Cache Architectures. MICRO 2006: 15-25
9EEDebjit Sinha, Narendra V. Shenoy, Hai Zhou: Statistical Timing Yield Optimization by Gate Sizing. IEEE Trans. VLSI Syst. 14(10): 1140-1146 (2006)
8EEDebjit Sinha, Hai Zhou: Statistical Timing Analysis With Coupling. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2965-2975 (2006)
7EEDebjit Sinha, Hai Zhou: Gate-size optimization under timing constraints for coupling-noise reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1064-1074 (2006)
2005
6EEDebjit Sinha, Hai Zhou: Yield driven gate sizing for coupling-noise reduction under uncertainty. ASP-DAC 2005: 192-197
5 Debjit Sinha, Narendra V. Shenoy, Hai Zhou: Statistical gate sizing for timing yield optimization. ICCAD 2005: 1037-1041
4 Debjit Sinha, Hai Zhou: A unified framework for statistical timing analysis with coupling and multiple input switching. ICCAD 2005: 837-843
2004
3EESanghamitra Roy, Debjit Sinha, Prithviraj Banerjee: An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design. FPGA 2004: 256
2EEDebjit Sinha, Hai Zhou: Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation. ICCAD 2004: 14-19
1EEDebjit Sinha, Hai Zhou, Chris C. N. Chu: Optimal gate sizing for coupling-noise reduction. ISPD 2004: 176-181

Coauthor Index

1Soroush Abbaspour [17] [18]
2Jonathan Adams [10]
3Prithviraj Banerjee (Prith Banerjee) [3] [13] [15]
4Revanta Banerji [18]
5Shabbir H. Batterywala [16]
6Frank Borkam [17]
7Chris C. N. Chu (Chris Chong-Nuen Chu) [1]
8Peter Feldmann [18]
9Hemlata Gupta [18]
10Yehea I. Ismail [12]
11DiaaEldin Khalil [12]
12Jianfeng Luo [16]
13Arindam Mallik [13] [15]
14Gokhan Memik [10]
15Serkan Ozdemir [10]
16Subramanian Rajagopalan [16]
17Sanghamitra Roy [3]
18Alex Rubin [17]
19Gregory Schaeffer [17] [18]
20Narendra V. Shenoy [5] [9] [11] [14] [16]
21Hai Zhou [1] [2] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)