Azadeh Davoodi

2008
32	EE	Tai-Hsuan Wu, Azadeh Davoodi: PaRS: fast and near-optimal grid-based cell sizing for library-based design. ICCAD 2008: 107-111
31	EE	Lin Xie, Azadeh Davoodi, Jun Zhang, Tai-Hsuan Wu: Adjustment-based modeling for statistical static timing analysis with high dimension of variability. ICCAD 2008: 181-184
30	EE	Anuj Kumar, Tai-Hsuan Wu, Azadeh Davoodi: SynECO: Incremental technology mapping with constrained placement and fast detail routing for predictable timing improvement. ICCD 2008: 551-556
29	EE	Jungseob Lee, Lin Xie, Azadeh Davoodi: A Dual-Vt low leakage SRAM array robust to process variations. ISCAS 2008: 580-583
28	EE	Tai-Hsuan Wu, Lin Xie, Azadeh Davoodi: A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing. ISLPED 2008: 45-50
27	EE	Lin Xie, Azadeh Davoodi: Robust Estimation of Timing Yield with Partial Statistical Information on Process Variations. ISQED 2008: 156-161
26	EE	Lin Xie, Azadeh Davoodi: Fast and Accurate Statistical Static Timing Analysis with Skewed Process Parameter Variation. ISQED 2008: 712-717
25	EE	Azadeh Davoodi, Ankur Srivastava: Variability Driven Gate Sizing for Binning Yield Optimization. IEEE Trans. VLSI Syst. 16(6): 683-692 (2008)
24	EE	Lin Xie, Azadeh Davoodi: Robust Estimation of Timing Yield With Partial Statistical Information on Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2264-2276 (2008)
2007
23	EE	Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak: Statistical timing analysis using Kernel smoothing. ICCD 2007: 97-102
22	EE	Jungseob Lee, Azadeh Davoodi: Comparison of Dual-Vt Configurations of SRAM Cell Considering Process-Induced Vt Variations. ISCAS 2007: 3018-3021
21	EE	Ashish Dobhal, Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava: Variability Driven Joint Leakage-Delay Optimization Through Gate Sizing with Provabale Convergence. VLSI Design 2007: 571-576
2006
20	EE	Azadeh Davoodi, Ankur Srivastava: Variability driven gate sizing for binning yield optimization. DAC 2006: 959-964
19	EE	Azadeh Davoodi, Ankur Srivastava: Probabilistic evaluation of solutions in variability-driven optimization. ISPD 2006: 17-24
18	EE	Azadeh Davoodi, Ankur Srivastava: Effective techniques for the generalized low-power binding problem. ACM Trans. Design Autom. Electr. Syst. 11(1): 52-69 (2006)
17	EE	Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava: Probabilistic Evaluation of Solutions in Variability-Driven Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 3010-3016 (2006)
16	EE	Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak: A statistical methodology for wire-length prediction. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1327-1336 (2006)
2005
15	EE	Azadeh Davoodi, Ankur Srivastava: Simultaneous floorplanning and resource binding: a probabilistic approach. ASP-DAC 2005: 517-522
14	EE	Azadeh Davoodi, Ankur Srivastava: Wake-up protocols for controlling current surges in MTCMOS-based technology. ASP-DAC 2005: 868-871
13	EE	Azadeh Davoodi, Ankur Srivastava: Variability-Driven Buffer Insertion Considering Correlations. ICCD 2005: 425-430
12	EE	Azadeh Davoodi, Ankur Srivastava: Probabilistic dual-Vth leakage optimization under variability. ISLPED 2005: 143-148
11	EE	Azadeh Davoodi, Ankur Srivastava: Voltage scheduling under unpredictabilities: a risk management paradigm. ACM Trans. Design Autom. Electr. Syst. 10(2): 354-368 (2005)
10	EE	Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava: Simultaneous V/sub t/ selection and assignment for leakage optimization. IEEE Trans. VLSI Syst. 13(6): 762-765 (2005)
9	EE	Azadeh Davoodi, Ankur Srivastava: Power-driven simultaneous resource binding and floorplanning: a probabilistic approach. IEEE Trans. VLSI Syst. 13(8): 934-942 (2005)
2004
8	EE	Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava: High level techniques for power-grid noise immunity. ACM Great Lakes Symposium on VLSI 2004: 13-18
7	EE	Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava: Variability inspired implementation selection problem. ICCAD 2004: 423-427
6	EE	Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava: Efficient statistical timing analysis through error budgeting. ICCAD 2004: 473-477
5	EE	Jennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak: Wire-length prediction using statistical techniques. ICCAD 2004: 702-705
4	EE	Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava: Empirical models for net-length probability distribution and applications. IEEE Trans. VLSI Syst. 12(10): 1066-1075 (2004)
2003
3	EE	Vishal Khandelwal, Azadeh Davoodi, Akash Nanavati, Ankur Srivastava: A Probabilistic Approach to Buffer Insertion. ICCAD 2003: 560-567
2	EE	Azadeh Davoodi, Ankur Srivastava: Effective graph theoretic techniques for the generalized low power binding problem. ISLPED 2003: 152-157
1	EE	Azadeh Davoodi, Ankur Srivastava: Voltage scheduling under unpredictabilities: a risk management paradigm. ISLPED 2003: 302-305

Coauthor Index

1	Ashish Dobhal	[21]
2	Vishal Khandelwal	[3] [4] [5] [6] [7] [8] [10] [16] [17] [21] [23]
3	Anuj Kumar	[30]
4	Jungseob Lee	[22] [29]
5	Akash Nanavati	[3]
6	Miodrag Potkonjak	[5] [16] [23]
7	Ankur Srivastava	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [23] [25]
8	Jennifer L. Wong	[5] [16] [23]
9	Tai-Hsuan Wu	[28] [30] [31] [32]
10	Lin Xie	[24] [26] [27] [28] [29] [31]
11	Jun Zhang	[31]

Colors in the list of coauthors