Kaijie Wu

2008
30	EE	Tongquan Wei, Piyush Mishra, Kaijie Wu, Han Liang: Fixed-Priority Allocation and Scheduling for Energy-Efficient Fault Tolerance in Hard Real-Time Multiprocessor Systems. IEEE Trans. Parallel Distrib. Syst. 19(11): 1511-1526 (2008)
2007
29	EE	Richard Stern, Nikhil Joshi, Kaijie Wu, Ramesh Karri: Register Transfer Level Concurrent Error Detection in Elliptic Curve Crypto Implementations. FDTC 2007: 112-119
28	EE	Han Liang, Piyush Mishra, Kaijie Wu: Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique. IEEE Trans. Computers 56(2): 243-252 (2007)
27	EE	Kyosun Kim, Kaijie Wu, Ramesh Karri: The Robust QCA Adder Designs Using Composable QCA Building Blocks. IEEE Trans. on CAD of Integrated Circuits and Systems 26(1): 176-183 (2007)
2006
26	EE	Tongquan Wei, Piyush Mishra, Kaijie Wu, Han Liang: Online task-scheduling for fault-tolerant low-energy real-time systems. ICCAD 2006: 522-527
25	EE	Nikhil Joshi, Jayachandran Sundararajan, Kaijie Wu, Bo Yang, Ramesh Karri: Tamper Proofing by Design Using Generalized Involution-Based Concurrent Error Detection for Involutional Substitution Permutation and Feistel Networks. IEEE Trans. Computers 55(10): 1230-1239 (2006)
24	EE	Bo Yang, Kaijie Wu, Ramesh Karri: Secure Scan: A Design-for-Test Architecture for Crypto Chips. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2287-2293 (2006)
23	EE	Kaijie Wu, Ramesh Karri: Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 413-422 (2006)
22	EE	Nikhil Joshi, Kaijie Wu, Jayachandran Sundararajan, Ramesh Karri: Concurrent error detection for involutional functions with applications in fault-tolerant cryptographic hardware design. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1163-1169 (2006)
21	EE	Kyosun Kim, Kaijie Wu, Ramesh Karri: Quantum-Dot Cellular Automata Design Guideline. IEICE Transactions 89-A(6): 1607-1614 (2006)
2005
20	EE	Tongquan Wei, Kaijie Wu, Ramesh Karri, Alex Orailoglu: Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands. ASP-DAC 2005: 1192-1195
19	EE	Bo Yang, Kaijie Wu, Ramesh Karri: Secure scan: a design-for-test architecture for crypto chips. DAC 2005: 135-140
18	EE	Kyosun Kim, Kaijie Wu, Ramesh Karri: owards Designing Robust QCA Architectures in the Presence of Sneak Noise Paths. DATE 2005: 1214-1219
2004
17	EE	Nikhil Joshi, Kaijie Wu, Ramesh Karri: Concurrent Error Detection Schemes for Involution Ciphers. CHES 2004: 400-412
16	EE	Kaijie Wu, Ramesh Karri, Grigori Kuznetsov, Michael Gössel: Low Cost Concurrent Error Detection for the Advanced Encryption Standard. ITC 2004: 1242-1248
15	EE	Bo Yang, Kaijie Wu, Ramesh Karri: Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard. ITC 2004: 339-344
14	EE	Kaijie Wu, Ramesh Karri: Fault secure datapath synthesis using hybrid time and hardware redundancy. IEEE Trans. on CAD of Integrated Circuits and Systems 23(10): 1476-1485 (2004)
2003
13	EE	Kaijie Wu, Ramesh Karri: Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis. ITC 2003: 902-911
12	EE	Kaijie Wu, Ramesh Karri: Selectively breaking data dependences to improve the utilization of idle cycles in algorithm level re-computing data paths. IEEE Transactions on Reliability 52(4): 501-511 (2003)
11	EE	Kaijie Wu, Piyush Mishra, Ramesh Karri: Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit RC6 block cipher. Microelectronics Journal 34(1): 31-39 (2003)
2002
10	EE	Kaijie Wu, Ramesh Karri: Exploiting Idle Cycles for Algorithm Level Re-Computing. DATE 2002: 842-846
9	EE	Ramesh Karri, Kaijie Wu: Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique. IEEE Trans. VLSI Syst. 10(6): 864-875 (2002)
8	EE	Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim: Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers. IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1509-1517 (2002)
7	EE	Kaijie Wu, Ramesh Karri: Algorithm level recomputing using allocation diversity: a registertransfer level approach to time redundancy-based concurrent errordetection. IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1077-1087 (2002)
2001
6	EE	Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim: Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers. DAC 2001: 579-585
5	EE	Kaijie Wu, Ramesh Karri: Idle Cycles Based Concurrent Error Detection of RC6 Encryption. DFT 2001: 200-205
4	EE	Ramesh Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim: Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture. DFT 2001: 427-435
3	EE	Kaijie Wu, Ramesh Karri: Algorithm Level Re-Computing - A Register Transfer Level Concurrent Error Detection Technique. ICCAD 2001: 537-
2		Kaijie Wu, Ramesh Karri: Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection technique. ITC 2001: 221-229
2000
1		Ramesh Karri, Kaijie Wu: Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique. ITC 2000: 971-978

Coauthor Index

1	Michael Gössel	[16]
2	Nikhil Joshi	[17] [22] [25] [29]
3	Ramesh Karri	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [27] [29]
4	Kyosun Kim	[18] [21] [27]
5	Yongkook Kim	[4] [6] [8]
6	Grigori Kuznetsov	[16]
7	Han Liang	[26] [28] [30]
8	Piyush Mishra	[4] [6] [8] [11] [26] [28] [30]
9	Alex Orailoglu	[20]
10	Richard Stern	[29]
11	Jayachandran Sundararajan	[22] [25]
12	Tongquan Wei	[20] [26] [30]
13	Bo Yang	[15] [19] [24] [25]