Ivan S. Kourtev

2006
16	EE	Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones: Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). FCCM 2006: 299-300
15	EE	Baris Taskin, Ivan S. Kourtev: Delay Insertion Method in Clock Skew Scheduling. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 651-663 (2006)
14	EE	Joshua M. Lucas, Raymond Hoare, Ivan S. Kourtev, Alex K. Jones: Technology mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). Microprocessors and Microsystems 30(7): 445-456 (2006)
2005
13	EE	Baris Taskin, Ivan S. Kourtev: Delay insertion method in clock skew scheduling. ISPD 2005: 47-54
2004
12		Baris Taskin, Ivan S. Kourtev: Time borrowing and clock skew scheduling effects on multi-phase level-sensitive circuits. ISCAS (2) 2004: 617-620
11		Rajani Parthasarthy, Ivan S. Kourtev: Performance metrics for asynchronous digital circuits applicable to computer-aided design. ISCAS (5) 2004: 301-304
10		Baris Taskin, Ivan S. Kourtev: Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits. IEEE Trans. VLSI Syst. 12(1): 12-27 (2004)
9		Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Ivan S. Kourtev, Eby G. Friedman: Substrate coupling in digital circuits in mixed-signal smart-power systems. IEEE Trans. VLSI Syst. 12(1): 67-78 (2004)
2003
8	EE	Roy Mader, Ivan S. Kourtev: Reduced dynamic swing domino logic. ACM Great Lakes Symposium on VLSI 2003: 33-36
7	EE	Ivan S. Kourtev, Raymond R. Hoare, Steven P. Levitan, Tom Cain, Bruce R. Childers, Donald M. Chiarulli, David L. Landis: Short Courses in System-on-a-Chip (SoC) Design. MSE 2003: 126-127
6	EE	Herman Schmit, Thomas Kroll, Max Khusid, Ivan S. Kourtev, Narayanan Vijaykrishnan, David L. Landis: The Sandbox Design Experience Course. MSE 2003: 39-40
2002
5	EE	Roy Mader, Eby G. Friedman, Ami Litman, Ivan S. Kourtev: Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits. ISCAS (1) 2002: 357-360
4	EE	Baris Taskin, Ivan S. Kourtev: Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 111-118
3	EE	Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, V. Adler, F. Baez, Eby G. Friedman: Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling. Journal of Circuits, Systems, and Computers 11(3): 231-246 (2002)
1999
2	EE	Radu M. Secareanu, Ivan S. Kourtev, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman: Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems. Great Lakes Symposium on VLSI 1999: 314-317
1	EE	Ivan S. Kourtev, Eby G. Friedman: Clock skew scheduling for improved reliability via quadratic programming. ICCAD 1999: 239-243

Coauthor Index

1	V. Adler	[3]
2	F. Baez	[3]
3	Juan Becerra	[2] [9]
4	Cathie Burke	[9]
5	Tom Cain	[7]
6	Donald M. Chiarulli	[7]
7	Bruce R. Childers	[7]
8	Eby G. Friedman	[1] [2] [3] [5] [9]
9	Raymond R. Hoare (Raymond Hoare)	[7] [14] [16]
10	Alex K. Jones	[14] [16]
11	Max Khusid	[6]
12	Thomas Kroll	[6]
13	David L. Landis	[6] [7]
14	Steven P. Levitan	[7]
15	Ami Litman	[5]
16	Joshua M. Lucas	[14]
17	Roy Mader	[5] [8]
18	Christopher Morton	[2] [9]
19	Rajani Parthasarthy	[11]
20	Herman Schmit	[6]
21	Scott Seabridge	[9]
22	Radu M. Secareanu	[2] [9]
23	William Staub	[2] [9]
24	Kevin T. Tang	[3]
25	Baris Taskin	[4] [10] [12] [13] [15]
26	Thomas Tellier	[2] [9]
27	Dimitrios Velenis	[3]
28	Narayanan Vijaykrishnan (Vijaykrishnan Narayanan)	[6]
29	Scott Warner	[9]
30	Thomas E. Watrobski	[2] [9]

Colors in the list of coauthors