Fei Sun

2008
13	EE	Yang Liu, Fei Sun, Tong Zhang: Energy-efficient soft-output trellis decoder design using trellis quasi-reduction and importance-aware clock skew scheduling. ISCAS 2008: 740-743
2007
12	EE	Fei Sun, Chien-Liang Fok, Gruia-Catalin Roman: sChat: a group communication service over wireless sensor networks. IPSN 2007: 543-544
11	EE	Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2035-2045 (2007)
2006
10	EE	Fei Sun, Tong Zhang: Low power state-parallel relaxed adaptive Viterbi decoder design and implementation. ISCAS 2006
9	EE	Fei Sun, Siddharth Devarajan, Kenneth Rose, Tong Zhang: Multilevel flash memory on-chip error correction based on trellis coded modulation. ISCAS 2006
8	EE	Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors. VLSI Design 2006: 473-476
7	EE	Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: A Scalable Synthesis Methodology for Application-Specific Processors. IEEE Trans. VLSI Syst. 14(11): 1175-1188 (2006)
6	EE	Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Application-specific heterogeneous multiprocessor synthesis using extensible processors. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1589-1602 (2006)
2005
5	EE	Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors. VLSI Design 2005: 551-556
4	EE	Fei Sun, Tong Zhang: Parallel high-throughput limited search trellis decoder VLSI design. IEEE Trans. VLSI Syst. 13(9): 1013-1022 (2005)
2004
3	EE	Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Custom-instruction synthesis for extensible-processor platforms. IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 216-228 (2004)
2003
2	EE	Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: A Scalable Application-Specific Processor Synthesis Methodology. ICCAD 2003: 283-290
2002
1	EE	Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha: Synthesis of custom processors based on extensible platforms. ICCAD 2002: 641-648

Coauthor Index

1	Siddharth Devarajan	[9]
2	Chien-Liang Fok	[12]
3	Niraj K. Jha	[1] [2] [3] [5] [6] [7] [8] [11]
4	Yang Liu	[13]
5	Anand Raghunathan	[1] [2] [3] [5] [6] [7] [8] [11]
6	Srivaths Ravi	[1] [2] [3] [5] [6] [7] [8] [11]
7	Gruia-Catalin Roman	[12]
8	Kenneth Rose	[9]
9	Tong Zhang	[4] [9] [10] [13]

Colors in the list of coauthors