Keunwoo Kim

2008
15	EE	Saibal Mukhopadhyay, Rajiv V. Joshi, Keunwoo Kim, Ching-Te Chuang: Variability Analysis for sub-100nm PD/SOI Sense-Amplifier. ISQED 2008: 488-491
14	EE	Rouwaida Kanj, Rajiv V. Joshi, Keunwoo Kim, Richard Williams, Sani R. Nassif: Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield. ISQED 2008: 702-707
13	EE	Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy: Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. VLSI Design 2008: 125-130
12	EE	Jente B. Kuang, Keunwoo Kim, Ching-Te Chuang, Hung C. Ngo, F. H. Gebara, Kevin J. Nowka: Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies. IEEE Trans. VLSI Syst. 16(12): 1657-1665 (2008)
2007
11	EE	Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang: Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies. ISLPED 2007: 20-25
10	EE	Rajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Q. Williams, Ching-Te Chuang: A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies. ISLPED 2007: 8-13
9	EE	Jie Deng, Keunwoo Kim, Ching-Te Chuang, H.-S. Philip Wong: Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI. ISQED 2007: 145-152
8	EE	Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang: A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology. VLSI Design 2007: 665-672
7	EE	Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy: Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices. Microelectronics Journal 38(8-9): 931-941 (2007)
2006
6	EE	Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy: Modeling and Analysis of Leakage Currents in Double-Gate Technologies. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2052-2061 (2006)
2005
5	EE	Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy: Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits. ISLPED 2005: 8-13
4	EE	Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy: Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. ISQED 2005: 410-415
2004
3	EE	Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang: Nanoscale CMOS circuit leakage power reduction by double-gate device. ISLPED 2004: 102-107
2003
2	EE	Keunwoo Kim, Rajiv V. Joshi, Ching-Te Chuang: Strained-si devices and circuits for low-power applications. ISLPED 2003: 180-183
1	EE	Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim: Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits. ISQED 2003: 153-158

Coauthor Index

1	Aditya Bansal	[13]
2	Ching-Te Chuang	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [15]
3	Koushik K. Das	[3]
4	Jie Deng	[9]
5	F. H. Gebara	[12]
6	Rajiv V. Joshi	[1] [2] [3] [4] [7] [8] [10] [14] [15]
7	Rouwaida Kanj	[10] [14]
8	Jae-Joon Kim	[4] [7] [13]
9	Jente B. Kuang	[12]
10	Shih-Hsien Lo	[4] [7]
11	Saibal Mukhopadhyay	[4] [5] [6] [7] [11] [13] [15]
12	Sani R. Nassif	[14]
13	Hung C. Ngo	[12]
14	Edward J. Nowak	[8]
15	Kevin J. Nowka	[12]
16	Ruchir Puri	[1]
17	Kaushik Roy	[4] [5] [6] [7] [13]
18	Richard Williams	[14]
19	Richard Q. Williams	[8] [10]
20	H.-S. Philip Wong	[9]