| 2008 |
|---|
| 135 | EE | Manoj Kumar Goparaju,
Ashok Kumar Palaniswany,
Spyros Tragoudas:
A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks.
DFT 2008: 176-183 |
| 134 | EE | Rajsekhar Adapa,
Spyros Tragoudas:
Prioritization of Paths for Diagnosis.
DFT 2008: 474-481 |
| 133 | EE | Rajsekhar Adapa,
Edward Flanigan,
Spyros Tragoudas:
A Novel Test Generation Methodology for Adaptive Diagnosis.
ISQED 2008: 242-245 |
| 132 | EE | Michael N. Skoufis,
Kedar Karmarkar,
Themistoklis Haniotakis,
Spyros Tragoudas:
A High-Performance Bus Architecture for Strongly Coupled Interconnects.
ISQED 2008: 407-410 |
| 131 | EE | Edward Flanigan,
Arkan Abdulrahman,
Spyros Tragoudas:
Sequential Path Delay Fault Identification Using Encoded Delay Propagation Signatures.
ISQED 2008: 633-636 |
| 130 | EE | Manoj Kumar Goparaju,
Spyros Tragoudas:
A Novel ATPG Framework to Detect Weight Related Defects in Threshold Logic Gates.
VTS 2008: 323-328 |
| 129 | EE | Dimitri Kagaris,
Spyros Tragoudas:
Graph Theory and Algorithms.
Wiley Encyclopedia of Computer Science and Engineering 2008 |
| 128 | EE | Chunrong Song,
Spyros Tragoudas:
Identification of Critical Executable Paths at the Architectural Level.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2291-2302 (2008) |
| 127 | EE | Arkan Abdulrahman,
Spyros Tragoudas:
Low-power multi-core ATPG to target concurrency.
Integration 41(4): 459-473 (2008) |
| 126 | EE | Kyriakos Christou,
Maria K. Michael,
Spyros Tragoudas:
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation.
J. Electronic Testing 24(1-3): 203-222 (2008) |
| 2007 |
|---|
| 125 | EE | Michael N. Skoufis,
Haibo Wang,
Themistoklis Haniotakis,
Spyros Tragoudas:
Glitch Control with Dynamic Receiver Threshold Adjustment.
ISQED 2007: 410-415 |
| 124 | EE | Manoj Kumar Goparaju,
Spyros Tragoudas:
A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations.
ISQED 2007: 420-425 |
| 123 | EE | Rajsekhar Adapa,
Edward Flanigan,
Spyros Tragoudas,
Michael Laisne,
Hailong Cui,
Tsvetomir Petrov:
Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture.
ISQED 2007: 717-722 |
| 122 | EE | Edward Flanigan,
Spyros Tragoudas:
Enhanced Identification of Strong Robustly Testable Paths.
ISQED 2007: 729-736 |
| 121 | EE | Edward Flanigan,
Rajsekhar Adapa,
Hailong Cui,
Michael Laisne,
Spyros Tragoudas,
Tsvetomir Petrov:
Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture.
VLSI Design 2007: 805-812 |
| 120 | EE | Rajsekhar Adapa,
Spyros Tragoudas,
Maria K. Michael:
Accelerating Diagnosis via Dominance Relations between Sets of Faults.
VTS 2007: 219-224 |
| 119 | EE | Michalis D. Galanis,
Gregory Dimitroulakos,
Spyros Tragoudas,
Costas E. Goutis:
Speedups in embedded systems with a high-performance coprocessor datapath.
ACM Trans. Design Autom. Electr. Syst. 12(3): (2007) |
| 118 | EE | Khadija Stewart,
Spyros Tragoudas:
Managing the power resources of sensor networks with performance considerations.
Computer Communications 30(5): 1122-1135 (2007) |
| 117 | EE | Mahilchi Milir Vaseekar Kumar,
Spyros Tragoudas:
High-Quality Transition Fault ATPG for Small Delay Defects.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 983-989 (2007) |
| 2006 |
|---|
| 116 | EE | Sandeep Dechu,
Manoj Kumar Goparaju,
Spyros Tragoudas:
A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates.
DFT 2006: 318-326 |
| 115 | EE | Kyriakos Christou,
Maria K. Michael,
Spyros Tragoudas:
Implicit Critical PDF Test Generation with Maximal Test Efficiency.
DFT 2006: 50-58 |
| 114 | EE | Stelios Neophytou,
Maria K. Michael,
Spyros Tragoudas:
Efficient Deterministic Test Generation for BIST Schemes with LFSR Reseeding.
IOLTS 2006: 43-50 |
| 113 | EE | Rajsekhar Adapa,
Spyros Tragoudas,
Maria K. Michael:
Sub-faults identification for collapsing in diagnosis.
ISCAS 2006 |
| 112 | EE | Krishna Prasad Raghuraman,
Haibo Wang,
Spyros Tragoudas:
Minimizing FPGA Reconfiguration Data at Logic Level.
ISQED 2006: 219-224 |
| 111 | EE | Arkan Abdulrahman,
Spyros Tragoudas:
Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level.
ISQED 2006: 300-305 |
| 110 | EE | Rajsekhar Adapa,
Spyros Tragoudas,
Maria K. Michael:
Evaluation of Collapsing Methods for Fault Diagnosis.
ISQED 2006: 439-444 |
| 109 | EE | Edward Flanigan,
Themistoklis Haniotakis,
Spyros Tragoudas:
An Improved Method for Identifying Linear Dependencies in Path Delay Faults.
ISQED 2006: 457-462 |
| 108 | EE | Khadija Stewart,
Spyros Tragoudas:
Interconnect Testing for Networks on Chips.
VTS 2006: 100-107 |
| 107 | EE | Saravanan Padmanaban,
Spyros Tragoudas:
Implicit grading of multiple path delay faults.
ACM Trans. Design Autom. Electr. Syst. 11(2): 346-361 (2006) |
| 106 | EE | Dimitri Kagaris,
Spyros Tragoudas,
Sherin Kuriakose:
InTeRail: A Test Architecture for Core-Based SOCs.
IEEE Trans. Computers 55(2): 137-149 (2006) |
| 105 | EE | Mahilchi Milir Vaseekar Kumar,
Spyros Tragoudas,
Sreejit Chakravarty,
Rathish Jayabharathi:
Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2954-2964 (2006) |
| 104 | EE | Stelios Neophytou,
Maria K. Michael,
Spyros Tragoudas:
Functions for Quality Transition-Fault Tests and Their Applications in Test-Set Enhancement.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 3026-3035 (2006) |
| 103 | EE | Michalis D. Galanis,
George Theodoridis,
Spyros Tragoudas,
Constantinos E. Goutis:
A high-performance data path for synthesizing DSP kernels.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1154-1162 (2006) |
| 2005 |
|---|
| 102 | EE | Stelios Neophytou,
Maria K. Michael,
Spyros Tragoudas:
Test set enhancement for quality transition faults using function-based methods.
ACM Great Lakes Symposium on VLSI 2005: 182-187 |
| 101 | EE | Mahilchi Milir Vaseekar Kumar,
Spyros Tragoudas:
Low power test generation for path delay faults using stability functions.
ACM Great Lakes Symposium on VLSI 2005: 8-12 |
| 100 | EE | Mahilchi Milir Vaseekar Kumar,
Spyros Tragoudas,
Sreejit Chakravarty,
Rathish Jayabharathi:
Implicit and Exact Path Delay Fault Grading in Sequential Circuits.
DATE 2005: 990-995 |
| 99 | EE | Maria K. Michael,
Kyriakos Christou,
Spyros Tragoudas:
Towards finding path delay fault tests with high test efficiency using ZBDDs.
ICCD 2005: 464-467 |
| 98 | EE | Mahilchi Milir Vaseekar Kumar,
Spyros Tragoudas:
Quality Transition Fault Tests Suitable for Small Delay Defects.
ICCD 2005: 468-470 |
| 97 | EE | Khadija Stewart,
Themistoklis Haniotakis,
Spyros Tragoudas:
Design and Evaluation of a Security Scheme for Sensor Networks.
ISQED 2005: 197-201 |
| 96 | EE | M. Welling,
Spyros Tragoudas,
Haibo Wang:
A Minimum Cut Based Re-Synthesis Approach.
ISQED 2005: 202-207 |
| 95 | EE | Themistoklis Haniotakis,
Spyros Tragoudas,
G. Pani:
Reduced Test Application Time Based on Reachability Analysis.
ISQED 2005: 232-237 |
| 94 | EE | Maria K. Michael,
Stelios Neophytou,
Spyros Tragoudas:
Functions for Quality Transition Fault Tests.
ISQED 2005: 327-332 |
| 93 | EE | Krishna Prasad Raghuraman,
Haibo Wang,
Spyros Tragoudas:
A Novel Approach to Minimizing Reconfiguration Cost for LUT-Based FPGAs.
VLSI Design 2005: 673-676 |
| 92 | EE | Maria K. Michael,
Spyros Tragoudas:
Function-based compact test pattern generation for path delay faults.
IEEE Trans. VLSI Syst. 13(8): 996-1001 (2005) |
| 91 | EE | Saravanan Padmanaban,
Spyros Tragoudas:
Efficient identification of (critical) testable path delay faults using decision diagrams.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(1): 77-87 (2005) |
| 90 | EE | Spyros Tragoudas,
Vijay Nagarandal:
On-chip embedding mechanisms for large sets of vectors for delay test.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 488-497 (2005) |
| 89 | EE | M. Moiz Khan,
Spyros Tragoudas:
Rewiring for watermarking digital circuit netlists.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1132-1137 (2005) |
| 88 | EE | Mahilchi Milir Vaseekar Kumar,
Spyros Tragoudas:
Low Power Test Generation for Path Delay Faults.
J. Low Power Electronics 1(2): 194-205 (2005) |
| 87 | EE | Michalis D. Galanis,
George Theodoridis,
Spyros Tragoudas,
Constantinos E. Goutis:
A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels.
Journal of Circuits, Systems, and Computers 14(4): 877-893 (2005) |
| 2004 |
|---|
| 86 | EE | Mahilchi Milir Vaseekar Kumar,
Saravanan Padmanaban,
Spyros Tragoudas:
Low power ATPG for path delay faults.
ACM Great Lakes Symposium on VLSI 2004: 389-392 |
| 85 | EE | Saravanan Padmanaban,
Spyros Tragoudas:
Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults.
DATE 2004: 50-55 |
| 84 | EE | Michalis D. Galanis,
George Theodoridis,
Spyros Tragoudas,
Dimitrios Soudris,
Constantinos E. Goutis:
Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path.
FCCM 2004: 275-276 |
| 83 | EE | Michalis D. Galanis,
George Theodoridis,
Spyros Tragoudas,
Dimitrios Soudris,
Constantinos E. Goutis:
A novel coarse-grain reconfigurable data-path for accelerating DSP kernels.
FPGA 2004: 252 |
| 82 | EE | Michalis D. Galanis,
George Theodoridis,
Spyros Tragoudas,
Dimitrios Soudris,
Constantinos E. Goutis:
Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path.
FPL 2004: 868-873 |
| 81 | EE | M. Moiz Khan,
Spyros Tragoudas:
Rewiring for Watermarking Digital Circuits.
ISQED 2004: 143-148 |
| 80 | EE | Saravanan Padmanaban,
Spyros Tragoudas:
An Adaptive Path Delay Fault Diagnosis Methodology.
ISQED 2004: 491-496 |
| 79 | EE | Haibo Wang,
Suchitra Kulkarni,
Spyros Tragoudas:
On-line Testing Field Programmable Analog Array Circuits.
ITC 2004: 1340-1348 |
| 78 | EE | Saravanan Padmanaban,
Spyros Tragoudas:
A Critical Path Selection Method for Delay Testing.
ITC 2004: 232-241 |
| 77 | EE | Arkan Abdulrahman,
Spyros Tragoudas:
Compact ATPG for Concurrent SOC Testing.
MTV 2004: 16-21 |
| 76 | EE | M. Moiz Khan,
Spyros Tragoudas,
Magdy S. Abadir,
Jiang Brandon Liu:
Identification of Gates for Covering all Critical Paths.
MTV 2004: 92-96 |
| 75 | EE | Michalis D. Galanis,
George Theodoridis,
Spyros Tragoudas,
Dimitrios Soudris,
Constantinos E. Goutis:
Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path.
PATMOS 2004: 652-661 |
| 74 | EE | Michalis D. Galanis,
George Theodoridis,
Spyros Tragoudas,
Dimitrios Soudris,
Costas E. Goutis:
A Novel Data-Path for Accelerating DSP Kernels.
SAMOS 2004: 363-372 |
| 73 | EE | J. V. Deodhar,
Spyros Tragoudas:
Implicit deductive fault simulation for complex delay fault models.
IEEE Trans. VLSI Syst. 12(6): 636-641 (2004) |
| 72 | EE | Maria K. Michael,
Themistoklis Haniotakis,
Spyros Tragoudas:
A unified framework for generating all propagation functions for logic errors and events.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(6): 980-986 (2004) |
| 2003 |
|---|
| 71 | EE | Saravanan Padmanaban,
Spyros Tragoudas:
Non-Enumerative Path Delay Fault Diagnosis .
DATE 2003: 10322-10327 |
| 70 | EE | Dimitri Kagaris,
Spyros Tragoudas:
InTeRail: Using Existing and Extra Interconnects to Test Core-Based SOCs.
IOLTS 2003: 219-224 |
| 69 | EE | Maria K. Michael,
Spyros Tragoudas:
Generation of Hazard Identification Functions.
ISQED 2003: 419-424 |
| 68 | EE | Spyros Tragoudas,
N. Denny:
Path delay fault testing using test points.
ACM Trans. Design Autom. Electr. Syst. 8(1): 1-10 (2003) |
| 67 | EE | Saravanan Padmanaban,
Spyros Tragoudas:
An implicit path-delay fault diagnosis methodology.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1399-1408 (2003) |
| 66 | EE | Saravanan Padmanaban,
Maria K. Michael,
Spyros Tragoudas:
Exact path delay fault coverage with fundamental ZBDD operations.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 305-316 (2003) |
| 65 | EE | Dimitri Kagaris,
Spyros Tragoudas:
LFSR Characteristic Polynomials for Pseudo-Exhaustive TPG with Low Number of Seeds.
J. Electronic Testing 19(3): 233-244 (2003) |
| 2002 |
|---|
| 64 | EE | Saravanan Padmanaban,
Spyros Tragoudas:
Exact Grading of Multiple Path Delay Faults.
DATE 2002: 84-88 |
| 63 | EE | Maria K. Michael,
Spyros Tragoudas:
ATPG tools for delay faults at the functional level.
ACM Trans. Design Autom. Electr. Syst. 7(1): 33-57 (2002) |
| 62 | EE | Turgay Korkmaz,
Marwan Krunz,
Spyros Tragoudas:
An efficient algorithm for finding a path subject to two additive constraints.
Computer Communications 25(3): 225-238 (2002) |
| 61 | | Spyros Tragoudas,
Yaakov L. Varol:
Disjoint Paths with Length Constraints.
I. J. Comput. Appl. 9(3): 158-166 (2002) |
| 60 | EE | Xrysovalantis Kavousianos,
Dimitris Bakalis,
Dimitris Nikolos,
Spyros Tragoudas:
A new built-in TPG method for circuits with random patternresistant faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(7): 859-866 (2002) |
| 59 | EE | Dimitrios Kagaris,
Spyros Tragoudas:
On the nonenumerative path delay fault simulation problem.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1095-1101 (2002) |
| 58 | EE | Dimitrios Kagaris,
Spyros Tragoudas:
Using a WLFSR to Embed Test Pattern Pairs in Minimum Time.
J. Electronic Testing 18(3): 305-313 (2002) |
| 2001 |
|---|
| 57 | EE | Dimitri Kagaris,
Spyros Tragoudas:
Using a WLFSR to Embed Test Pattern Pairs in Minimum Time.
IOLTW 2001: 75-79 |
| 56 | EE | Jayant Deodhar,
Spyros Tragoudas:
Color Counting and its Application to Path Delay Fault Coverage.
ISQED 2001: 378-383 |
| 55 | EE | Maria K. Michael,
Spyros Tragoudas:
ATPG for Path Delay Faults without Path Enumeration.
ISQED 2001: 384- |
| 54 | | Saravanan Padmanaban,
Maria K. Michael,
Spyros Tragoudas:
Exact path delay grading with fundamental BDD operations.
ITC 2001: 642-651 |
| 53 | EE | Dimitrios Kagaris,
Spyros Tragoudas:
Von Neumann hybrid cellular automata for generating deterministic test sequences.
ACM Trans. Design Autom. Electr. Syst. 6(3): 308-321 (2001) |
| 52 | | Dimitrios Kagaris,
Spyros Tragoudas:
Computational analysis of counter-based schemes for VLSI test pattern generation.
Discrete Applied Mathematics 110(2-3): 227-250 (2001) |
| 2000 |
|---|
| 51 | EE | Dimitrios Kagaris,
Spyros Tragoudas:
Pseudoexhaustive TPG with a Provably Low Number of LFSR Seeds.
ICCD 2000: 42-47 |
| 50 | EE | Turgay Korkmaz,
Marwan Krunz,
Spyros Tragoudas:
An efficient algorithm for finding a path subject to two additive constraints.
SIGMETRICS 2000: 318-327 |
| 49 | EE | Dimitri Kagaris,
Spyros Tragoudas,
Amitava Majumdar:
Test-set partitioning for multi-weighted random LFSRs.
Integration 30(1): 65-75 (2000) |
| 1999 |
|---|
| 48 | | Spyros Tragoudas,
Yaakov L. Varol:
Disjoint paths with length constraints.
Computers and Their Applications 1999: 277-280 |
| 47 | EE | Spyros Tragoudas,
Maria K. Michael:
ATPG Tools for Delay Faults at the Functional Level.
DATE 1999: 631- |
| 46 | EE | Dimitrios Kagaris,
Spyros Tragoudas:
LFSR/SR Pseudo-Exhaustive TPG in Fewer Test Cycles.
DFT 1999: 130-138 |
| 45 | EE | Spyros Tragoudas,
N. Denny:
Testing for Path Delay Faults Using Test Points.
DFT 1999: 86-94 |
| 44 | EE | Spyros Tragoudas,
Maria K. Michael:
Functional ATPG for Delay Faults.
Great Lakes Symposium on VLSI 1999: 16-19 |
| 43 | EE | Spyros Tragoudas:
The most reliable data path transmission.
IPCCC 1999: 15-19 |
| 42 | EE | Dimitrios Kagaris,
Spyros Tragoudas:
Embedded cores using built-in mechanisms.
ISCAS (1) 1999: 23-26 |
| 41 | | Spyros Tragoudas:
Accurate path delay fault coverage is feasible.
ITC 1999: 201-210 |
| 40 | EE | Dimitrios Kagaris,
Spyros Tragoudas:
On the design of optimal counter-based schemes for test set embedding.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 219-230 (1999) |
| 39 | EE | Spyros Tragoudas,
Dimitrios Karayiannis:
A fast nonenumerative automatic test pattern generator for pathdelay faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(7): 1050-1057 (1999) |
| 38 | EE | Dimitri Kagaris,
Spyros Tragoudas:
Maximum weighted independent sets on transitive graphs and applications1.
Integration 27(1): 77-86 (1999) |
| 37 | EE | Dimitrios Kagaris,
Grammati E. Pantziou,
Spyros Tragoudas,
Christos D. Zaroliagis:
Transmissions in a network with capacities and delays.
Networks 33(3): 167-174 (1999) |
| 1998 |
|---|
| 36 | EE | Dimitrios Kagaris,
Spyros Tragoudas,
Amitava Majumdar:
On-Chip Test Embedding for Multi-Weighted Random LFSRs.
DFT 1998: 135- |
| 35 | EE | Dimitrios Karayiannis,
Spyros Tragoudas:
A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults.
VTS 1998: 440-445 |
| 1997 |
|---|
| 34 | EE | Dimitrios Kagaris,
Spyros Tragoudas:
Cellular automata for generating deterministic test sequences.
ED&TC 1997: 77-81 |
| 33 | EE | Dimitrios Kagaris,
Spyros Tragoudas:
Maximum independent sets on transitive graphs and their applications in testing and CAD.
ICCAD 1997: 736-740 |
| 32 | | Dimitrios Kagaris,
Spyros Tragoudas,
Dimitrios Karayiannis:
Nonenumerative Path Delay Fault Coverage Estimation with Optimal Algorithms.
ICCD 1997: 366-371 |
| 31 | EE | Dimitrios Kagaris,
Spyros Tragoudas,
Dimitrios Karayiannis:
Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 309-315 (1997) |
| 30 | EE | Spyros Tragoudas,
Dimitrios Karayiannis:
Implementing and clustering modules with complex delays.
Integration 22(1-2): 39-57 (1997) |
| 1996 |
|---|
| 29 | EE | Dimitrios Kagaris,
Spyros Tragoudas:
A multiseed counter TPG with performance guarantee.
ICCD 1996: 34-39 |
| 28 | EE | D. Kuguris,
Spyros Tragoudas:
FPGA Module Minimization.
ICCD 1996: 566-571 |
| 27 | | Dimitrios Karayiannis,
Spyros Tragoudas:
ATPD: An Automatic Test Pattern Generator for Path Delay Faults.
ITC 1996: 443-452 |
| 26 | EE | Dimitrios Kagaris,
Spyros Tragoudas:
Generating deterministic unordered test patterns with counters.
VTS 1996: 374-379 |
| 25 | | Spyros Tragoudas,
Yaakov L. Varol:
Computing Disjoint Path with Lenght Constraints.
WG 1996: 375-389 |
| 24 | EE | Dimitrios Kagaris,
Spyros Tragoudas:
A fast algorithm for minimizing FPGA combinational and sequential modules.
ACM Trans. Design Autom. Electr. Syst. 1(3): 341-351 (1996) |
| 23 | | Dimitrios Kagaris,
Spyros Tragoudas:
Retiming-Based Partial Scan.
IEEE Trans. Computers 45(1): 75-87 (1996) |
| 22 | | Dimitrios Kagaris,
Spyros Tragoudas,
Amitava Majumdar:
On the Use of Counters for Reproducing Deterministic Test Sets.
IEEE Trans. Computers 45(12): 1405-1419 (1996) |
| 21 | | Spyros Tragoudas:
Min-Cut Partitioning on Underlying Tree and Graph Structures.
IEEE Trans. Computers 45(4): 470-474 (1996) |
| 20 | | Spyros Tragoudas:
Improved Approximations for the Minimum-Cut Ratio and the Flux.
Mathematical Systems Theory 29(2): 157-167 (1996) |
| 1995 |
|---|
| 19 | EE | Dimitrios Karayiannis,
Spyros Tragoudas:
Uniform area timing-driven circuit implementation.
Great Lakes Symposium on VLSI 1995: 2-7 |
| 18 | EE | Dimitrios Kagaris,
Spyros Tragoudas,
Grammati E. Pantziou,
Christos D. Zaroliagis:
Quickest paths: parallelization and dynamization .
HICSS (2) 1995: 39-40 |
| 17 | | Dimitrios Kagaris,
Spyros Tragoudas,
Grammati E. Pantziou,
Christos D. Zaroliagis:
On the Computation of Fast Data Transmissions in Networks with Capacities and Delays.
WADS 1995: 291-302 |
| 16 | EE | Dimitrios Kagaris,
Spyros Tragoudas,
Dinesh Bhatia:
Pseudo-exhaustive built-in TPG for sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1160-1171 (1995) |
| 15 | | James Haralambides,
Spyros Tragoudas:
Bipartitioning into Overlapping Sets.
Int. J. Found. Comput. Sci. 6(1): 67-88 (1995) |
| 14 | | Frank Thomson Leighton,
Fillia Makedon,
Serge A. Plotkin,
Clifford Stein,
Éva Stein,
Spyros Tragoudas:
Fast Approximation Algorithms for Multicommodity Flow Problems.
J. Comput. Syst. Sci. 50(2): 228-243 (1995) |
| 13 | EE | Dimitrios Kagaris,
Spyros Tragoudas:
Avoiding linear dependencies in LFSR test pattern generators.
J. Electronic Testing 6(2): 229-241 (1995) |
| 1994 |
|---|
| 12 | | Dimitrios Kagaris,
Spyros Tragoudas:
A Class of Good Characteristics Polynomials for LFSR Test Pattern Generators.
ICCD 1994: 292-295 |
| 11 | | Jim E. Crenshaw,
Spyros Tragoudas,
Naveed A. Sherwani:
High Performance Over-the-Cell Routing.
VLSI Design 1994: 137-142 |
| 10 | EE | Dimitrios Kagaris,
Fillia Makedon,
Spyros Tragoudas:
A method for pseudo-exhaustive test pattern generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(9): 1170-1178 (1994) |
| 1993 |
|---|
| 9 | EE | Dimitrios Kagaris,
Spyros Tragoudas:
Partial Scan with Retiming.
DAC 1993: 249-254 |
| 8 | | Dimitrios Kagaris,
Spyros Tragoudas,
Dinesh Bhatia:
Pseudoexhaustive BIST for Sequential Circuits.
ICCD 1993: 523-527 |
| 7 | EE | Dimitrios Kagaris,
Spyros Tragoudas:
Cost-effective LFSR synthesis for optimal pseudoexhaustive BIST test sets.
IEEE Trans. VLSI Syst. 1(4): 526-536 (1993) |
| 6 | | Antonios Symvonis,
Spyros Tragoudas:
Searching a Pseudo 3-Sided Solid Orthoconvex Grid.
Int. J. Found. Comput. Sci. 4(4): 325-353 (1993) |
| 1992 |
|---|
| 5 | | Dimitrios Kagaris,
Fillia Makedon,
Spyros Tragoudas:
On Minimizing Hardware Overhead for Pseudoexhaustive Circuit Testability.
ICCD 1992: 358-364 |
| 4 | | Antonios Symvonis,
Spyros Tragoudas:
Searching a Solid Pseudo 3-Sided Orthoconvex Grid.
ISAAC 1992: 188-197 |
| 1991 |
|---|
| 3 | | Frank Thomson Leighton,
Fillia Makedon,
Serge A. Plotkin,
Clifford Stein,
Éva Tardos,
Spyros Tragoudas:
Fast Approximation Algorithms for Multicommodity Flow Problems
STOC 1991: 101-111 |
| 2 | EE | Panayiotis E. Pintelas,
Spyros Tragoudas:
A comparative study of five language independent programming environments.
Journal of Systems and Software 14(1): 3-15 (1991) |
| 1990 |
|---|
| 1 | | Fillia Makedon,
Spyros Tragoudas:
Approximating the minimum net expansion: Near optimal solutions to circuit partitioning problems.
WG 1990: 140-153 |
