| 2008 |
|---|
| 25 | EE | John D. Crabtree,
Dinesh P. Mehta:
Automated reaction mapping.
ACM Journal of Experimental Algorithmics 13: (2008) |
| 2006 |
|---|
| 24 | EE | Yan Feng,
Dinesh P. Mehta:
Heterogeneous Floorplanning for FPGAs.
VLSI Design 2006: 257-262 |
| 23 | EE | Yan Feng,
Dinesh P. Mehta:
Module relocation to obtain feasible constrained floorplans.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 856-866 (2006) |
| 2004 |
|---|
| 22 | EE | Yan Feng,
Dinesh P. Mehta:
Constrained Floorplanning with Whitespace.
VLSI Design 2004: 969-974 |
| 21 | EE | Kun Gao,
Dinesh P. Mehta:
Floorplan Classification Algorithms.
VLSI Design 2004: 975-980 |
| 20 | EE | Brad Williams,
Dinesh P. Mehta,
Tracy Camp,
William Navidi:
Predictive Models to Rebroadcast in Mobile Ad Hoc Networks.
IEEE Trans. Mob. Comput. 3(3): 295-303 (2004) |
| 19 | EE | Yan Feng,
Dinesh P. Mehta,
Hannah Honghua Yang:
Constrained floorplanning using network flows.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 572-580 (2004) |
| 18 | EE | Sahar Idwan,
Dinesh P. Mehta,
Mario A. Lopez:
Fast Pursuit Of Mobile Nodes Using TPR Trees.
Int. J. Found. Comput. Sci. 15(5): 753-772 (2004) |
| 2003 |
|---|
| 17 | EE | Yan Feng,
Dinesh P. Mehta,
Hannah Honghua Yang:
Constrained "Modern" Floorplanning.
ISPD 2003: 128-135 |
| 2002 |
|---|
| 16 | EE | Krishna M. Kavi,
Dinesh P. Mehta:
Mutual Exclusion on Optical Buses.
Parallel Processing Letters 12(3-4): 341-358 (2002) |
| 15 | EE | Dinesh P. Mehta,
Vijay Raghavan:
Decision tree approximations of Boolean functions.
Theor. Comput. Sci. 270(1-2): 609-623 (2002) |
| 2001 |
|---|
| 14 | EE | Swanwa Liao,
Mario A. Lopez,
Dinesh P. Mehta:
Constrained polygon transformations for incremental floorplanning.
ACM Trans. Design Autom. Electr. Syst. 6(3): 322-342 (2001) |
| 2000 |
|---|
| 13 | | Dinesh P. Mehta,
Vijay Raghavan:
Decision Tree Approximations of Boolean Functions.
COLT 2000: 16-24 |
| 12 | EE | Dinesh P. Mehta,
Naveed A. Sherwani:
On the use of flexible, rectilinear blocks to obtain minimum-area floorplans in mixed block and cell designs.
ACM Trans. Design Autom. Electr. Syst. 5(1): 82-97 (2000) |
| 1998 |
|---|
| 11 | EE | Dinesh P. Mehta:
Estimating the storage requirements of the rectangular and L-shaped corner stitching data structures.
ACM Trans. Design Autom. Electr. Syst. 3(2): 272-284 (1998) |
| 10 | | Dinesh P. Mehta,
Erica D. Wilson:
Parallel algorithms for corner stitching.
Concurrency - Practice and Experience 10(15): 1317-1341 (1998) |
| 1997 |
|---|
| 9 | EE | Dinesh P. Mehta,
Naveed A. Sherwani,
A. Bariya:
T3: Physical Design.
VLSI Design 1997: 3- |
| 8 | EE | Dinesh P. Mehta,
George Blust:
Corner stitching for simple rectilinear shapes [VLSI layouts].
IEEE Trans. on CAD of Integrated Circuits and Systems 16(2): 186-198 (1997) |
| 7 | EE | Dinesh P. Mehta,
Sartaj K. Sahni:
Models, techniques, and algorithms for finding, selecting, and displaying patterns in strings and other discrete objects.
Journal of Systems and Software 39(3): 201-221 (1997) |
| 1996 |
|---|
| 6 | EE | Mario A. Lopez,
Dinesh P. Mehta:
Partitioning Algorithms for Corner Stitching.
Great Lakes Symposium on VLSI 1996: 200- |
| 5 | EE | Dinesh P. Mehta,
Naveed A. Sherwani:
A Minimum-Area Floorplanning Algorithm for MBC Designs.
Great Lakes Symposium on VLSI 1996: 56-59 |
| 4 | EE | Mario A. Lopez,
Dinesh P. Mehta:
Efficient decomposition of polygons into L-shapes with application to VLSI layouts.
ACM Trans. Design Autom. Electr. Syst. 1(3): 371-395 (1996) |
| 1994 |
|---|
| 3 | | Dinesh P. Mehta,
Sartaj Sahni:
Computing Display Conflicts in String Visualization.
IEEE Trans. Computers 43(3): 350-361 (1994) |
| 1993 |
|---|
| 2 | | Dinesh P. Mehta,
Sartaj Sahni:
A Data Structure for Circular String Analysis and Visualization.
IEEE Trans. Computers 42(8): 992-997 (1993) |
| 1992 |
|---|
| 1 | | Dinesh P. Mehta,
Sartaj Sahni:
Computing Display Conflicts in String and Circular String Visualization.
CPM 1992: 244-261 |
