2008 |
12 | EE | Anand Rajaram,
David Z. Pan:
MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks.
ASP-DAC 2008: 250-257 |
11 | EE | Anand Rajaram,
David Z. Pan:
Robust chip-level clock tree synthesis for SOC designs.
DAC 2008: 720-723 |
10 | EE | Anand Rajaram,
Raguram Damodaran,
Arjun Rajagopal:
Practical Clock Tree Robustness Signoff Metrics.
ISQED 2008: 676-679 |
2007 |
9 | EE | Joon-Sung Yang,
Anand Rajaram,
Ninghy Shi,
Jian Chen,
David Z. Pan:
Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis.
ISQED 2007: 398-403 |
2006 |
8 | EE | Anand Rajaram,
David Z. Pan:
Variation tolerant buffered clock network synthesis with cross links.
ISPD 2006: 157-164 |
7 | EE | Anand Rajaram,
David Z. Pan:
Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction.
ISQED 2006: 79-84 |
6 | EE | Anand Rajaram,
Jiang Hu,
Rabi N. Mahapatra:
Reducing clock skew variability via crosslinks.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1176-1182 (2006) |
5 | EE | Anand Rajaram,
Bing Lu,
Jiang Hu,
Rabi N. Mahapatra,
Wei Guo:
Analytical bound for unwanted clock skew due to wire width variation.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1869-1876 (2006) |
2005 |
4 | | Ganesh Venkataraman,
Nikhil Jayakumar,
Jiang Hu,
Peng Li,
Sunil P. Khatri,
Anand Rajaram,
Patrick McGuinness,
Charles J. Alpert:
Practical techniques to reduce skew and its variations in buffered clock networks.
ICCAD 2005: 592-596 |
3 | EE | Anand Rajaram,
David Z. Pan,
Jiang Hu:
Improved algorithms for link-based non-tree clock networks for skew variability reduction.
ISPD 2005: 55-62 |
2004 |
2 | EE | Anand Rajaram,
Jiang Hu,
Rabi N. Mahapatra:
Reducing clock skew variability via cross links.
DAC 2004: 18-23 |
2003 |
1 | EE | Anand Rajaram,
Bing Lu,
Wei Guo,
Rabi N. Mahapatra,
Jiang Hu:
Analytical Bound for Unwanted Clock Skew due to Wire Width Variation.
ICCAD 2003: 401-407 |