| 2009 |
|---|
| 52 | | Fabrizio Lombardi,
Sanjukta Bhanja,
Yehia Massoud,
R. Iris Bahar:
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009
ACM 2009 |
| 51 | EE | Cesare Ferri,
R. Iris Bahar,
Mirko Loghi,
Massimo Poncino:
Energy-optimal synchronization primitives for single-chip multi-processors.
ACM Great Lakes Symposium on VLSI 2009: 141-144 |
| 50 | EE | Roto Le,
Sherief Reda,
R. Iris Bahar:
High-performance, cost-effective heterogeneous 3D FPGA architectures.
ACM Great Lakes Symposium on VLSI 2009: 251-256 |
| 49 | EE | Roto Le,
Sherief Reda,
R. Iris Bahar:
High-performance, cost-effective heterogeneous 3D FPGA architectures.
FPGA 2009: 286 |
| 2008 |
|---|
| 48 | EE | Cesare Ferri,
Amber Viescas,
Tali Moreshet,
R. Iris Bahar,
Maurice Herlihy:
Energy efficient synchronization techniques for embedded architectures.
ACM Great Lakes Symposium on VLSI 2008: 435-440 |
| 47 | EE | Andrea Calimera,
Enrico Macii,
Massimo Poncino,
R. Iris Bahar:
Temperature-insensitive synthesis using multi-vt libraries.
ACM Great Lakes Symposium on VLSI 2008: 5-10 |
| 46 | EE | Andrea Calimera,
R. Iris Bahar,
Enrico Macii,
Massimo Poncino:
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits.
ISLPED 2008: 217-220 |
| 45 | EE | Desta Tadesse,
R. Iris Bahar,
Joel Grodstein:
Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation.
VTS 2008: 339-344 |
| 44 | EE | R. Iris Bahar,
Krishnendu Chakrabarty:
Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies.
ACM Trans. Design Autom. Electr. Syst. 13(2): (2008) |
| 43 | EE | R. Iris Bahar,
Krishnendu Chakrabarty:
Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies.
JETC 4(2): (2008) |
| 42 | EE | Cesare Ferri,
Sherief Reda,
R. Iris Bahar:
Parametric yield management for 3D ICs: Models and strategies for improvement.
JETC 4(4): (2008) |
| 2007 |
|---|
| 41 | EE | Desta Tadesse,
D. Sheffield,
E. Lenge,
R. Iris Bahar,
Joel Grodstein:
Accurate timing analysis using SAT and pattern-dependent delay models.
DATE 2007: 1018-1023 |
| 40 | EE | Kundan Nepal,
R. Iris Bahar,
Joseph L. Mundy,
William R. Patterson,
Alexander Zaslavsky:
Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits.
DATE 2007: 576-581 |
| 39 | EE | Cesare Ferri,
Sherief Reda,
R. Iris Bahar:
Strategies for improving the parametric yield and profits of 3D ICs.
ICCAD 2007: 220-226 |
| 38 | EE | R. Iris Bahar,
Dan W. Hammerstrom,
Justin E. Harlow III,
William H. Joyner Jr.,
Clifford Lau,
Diana Marculescu,
Alex Orailoglu,
Massoud Pedram:
Architectures for Silicon Nanoelectronics and Beyond.
IEEE Computer 40(1): 25-33 (2007) |
| 37 | EE | Kundan Nepal,
R. Iris Bahar,
Joseph L. Mundy,
William R. Patterson,
Alexander Zaslavsky:
Designing Nanoscale Logic Circuits Based on Markov Random Fields.
J. Electronic Testing 23(2-3): 255-266 (2007) |
| 2006 |
|---|
| 36 | EE | Kundan Nepal,
R. Iris Bahar,
Joseph L. Mundy,
William R. Patterson,
Alexander Zaslavsky:
Optimizing noise-immune nanoscale circuits using principles of Markov random fields.
ACM Great Lakes Symposium on VLSI 2006: 149-152 |
| 35 | EE | Vladimir Stojanovic,
R. Iris Bahar,
Jennifer Dworak,
Richard Weiss:
A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors.
DAC 2006: 705-708 |
| 34 | EE | Kundan Nepal,
R. Iris Bahar,
Joseph L. Mundy,
William R. Patterson,
Alexander Zaslavsky:
Designing MRF based error correcting circuits for memory elements.
DATE 2006: 792-793 |
| 33 | EE | R. Iris Bahar:
Trends and Future Directions in Nano Structure Based Computing and Fabrication.
ICCD 2006 |
| 32 | EE | Tali Moreshet,
R. Iris Bahar,
Maurice Herlihy:
Energy implications of multiprocessor synchronization.
SPAA 2006: 329 |
| 31 | EE | Kundan Nepal,
R. Iris Bahar,
Joseph L. Mundy,
William R. Patterson,
Alexander Zaslavsky:
MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits.
IEEE Micro 26(5): 19-27 (2006) |
| 30 | EE | Hui-Yuan Song,
Kundan Nepal,
R. Iris Bahar,
Joel Grodstein:
Timing analysis for full-custom circuits using symbolic DC formulations.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1815-1830 (2006) |
| 2005 |
|---|
| 29 | EE | Kundan Nepal,
R. Iris Bahar,
Joseph L. Mundy,
William R. Patterson,
Alexander Zaslavsky:
Designing logic circuits for probabilistic computation in the presence of noise.
DAC 2005: 485-490 |
| 28 | EE | Tali Moreshet,
R. Iris Bahar,
Maurice Herlihy:
Energy reduction in multiprocessor systems using transactional memory.
ISLPED 2005: 331-334 |
| 27 | EE | R. Iris Bahar,
Mehdi Baradaran Tahoori,
Sandeep K. Shukla,
Fabrizio Lombardi:
Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale.
IEEE Design & Test of Computers 22(4): 295-297 (2005) |
| 26 | EE | R. Iris Bahar,
Hui-Yuan Song,
Kundan Nepal,
Joel Grodstein:
Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 502-515 (2005) |
| 2004 |
|---|
| 25 | EE | Kundan Nepal,
Hui-Yuan Song,
R. Iris Bahar,
Joel Grodstein:
RESTA: a robust and extendable symbolic timing analysis tool.
ACM Great Lakes Symposium on VLSI 2004: 407-412 |
| 24 | EE | Nikil Mehta,
Brian Singer,
R. Iris Bahar,
Michael Leuchtenburg,
Richard S. Weiss:
Fetch Halting on Critical Load Misses.
ICCD 2004: 244-249 |
| 23 | EE | Yu Bai,
R. Iris Bahar:
Reducing Issue Queue Power for Multimedia Applications using a Feedback Control Algorithm.
ICCD 2004: 54-57 |
| 22 | EE | Tali Moreshet,
R. Iris Bahar:
Effects of speculation on performance and issue queue design.
IEEE Trans. VLSI Syst. 12(10): 1123-1126 (2004) |
| 21 | EE | Yu Bai,
R. Iris Bahar:
A low-power in-order/out-of-order issue queue.
TACO 1(2): 152-179 (2004) |
| 2003 |
|---|
| 20 | EE | Tali Moreshet,
R. Iris Bahar:
Power-aware issue queue design for speculative instructions.
DAC 2003: 634-637 |
| 19 | EE | R. Iris Bahar,
Joseph L. Mundy,
Jie Chen:
A Probabilistic-Based Design Methodology for Nanoscale Computation.
ICCAD 2003: 480-486 |
| 18 | EE | Hui-Yuan Song,
S. Bohidar,
R. Iris Bahar,
Joel Grodstein:
Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current.
ICCD 2003: 70-75 |
| 17 | EE | Yu Bai,
R. Iris Bahar:
A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors.
ISVLSI 2003: 139-148 |
| 16 | EE | Eric Chi,
A. Michael Salem,
R. Iris Bahar,
Richard S. Weiss:
Combining Software and Hardware Monitoring for Improved Power and Performance Tuning.
Interaction between Compilers and Computer Architectures 2003: 57-64 |
| 2002 |
|---|
| 15 | | Hui-Yuan Song,
R. Iris Bahar,
Joel Grodstein:
Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations.
IWLS 2002: 203-208 |
| 2001 |
|---|
| 14 | EE | R. Iris Bahar,
Srilatha Manne:
Power and energy reduction via pipeline balancing.
ISCA 2001: 218-229 |
| 2000 |
|---|
| 13 | EE | Roberto Maro,
Yu Bai,
R. Iris Bahar:
Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors.
PACS 2000: 97-111 |
| 12 | EE | R. Iris Bahar,
Ernest T. Lampe,
Enrico Macii:
Power optimization of technology-dependent circuits based on symbolic computation of logic implications.
ACM Trans. Design Autom. Electr. Syst. 5(3): 267-293 (2000) |
| 1999 |
|---|
| 11 | EE | Brian R. Fisk,
R. Iris Bahar:
The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency.
ICCD 1999: 538-545 |
| 1998 |
|---|
| 10 | EE | R. Iris Bahar,
Gianluca Albera,
Srilatha Manne:
Power and performance tradeoffs using various caching strategies.
ISLPED 1998: 64-69 |
| 1997 |
|---|
| 9 | | R. Iris Bahar,
Erica A. Frohm,
Charles M. Gaona,
Gary D. Hachtel,
Enrico Macii,
Abelardo Pardo,
Fabio Somenzi:
Algebraic Decision Diagrams and Their Applications.
Formal Methods in System Design 10(2/3): 171-206 (1997) |
| 8 | EE | R. Iris Bahar,
Hyunwoo Cho,
Gary D. Hachtel,
Enrico Macii,
Fabio Somenzi:
Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1101-1115 (1997) |
| 1996 |
|---|
| 7 | EE | R. Iris Bahar,
M. Burns,
Gary D. Hachtel,
Enrico Macii,
H. Shin,
Fabio Somenzi:
Symbolic computation of logic implications for technology-dependent low-power synthesis.
ISLPED 1996: 163-168 |
| 1995 |
|---|
| 6 | EE | Srilatha Manne,
Abelardo Pardo,
R. Iris Bahar,
Gary D. Hachtel,
Fabio Somenzi,
Enrico Macii,
Massimo Poncino:
Computing the Maximum Power Cycles of a Sequential Circuit.
DAC 1995: 23-28 |
| 5 | EE | R. Iris Bahar,
Fabio Somenzi:
Boolean techniques for low power driven re-synthesis.
ICCAD 1995: 428-432 |
| 4 | EE | Abelardo Pardo,
R. Iris Bahar,
Srilatha Manne,
Peter Feldmann,
Gary D. Hachtel,
Fabio Somenzi:
CMOS dynamic power estimation based on collapsible current source transistor modeling.
ISLPD 1995: 111-116 |
| 1994 |
|---|
| 3 | | R. Iris Bahar,
Hyunwoo Cho,
Gary D. Hachtel,
Enrico Macii,
Fabio Somenzi:
Timing Analysis of Combinational Circuits using ADD's.
EDAC-ETC-EUROASIC 1994: 625-629 |
| 2 | EE | R. Iris Bahar,
Gary D. Hachtel,
Enrico Macii,
Fabio Somenzi:
A symbolic method to reduce power consumption of circuits containing false paths.
ICCAD 1994: 368-371 |
| 1993 |
|---|
| 1 | EE | R. Iris Bahar,
Erica A. Frohm,
Charles M. Gaona,
Gary D. Hachtel,
Enrico Macii,
Abelardo Pardo,
Fabio Somenzi:
Algebraic decision diagrams and their applications.
ICCAD 1993: 188-191 |
