| 2009 |
|---|
| 372 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Definition and application of approximate necessary assignments.
ACM Great Lakes Symposium on VLSI 2009: 105-108 |
| 371 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
State persistence: a property for guiding test generation.
ACM Great Lakes Symposium on VLSI 2009: 523-528 |
| 370 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Partitioned n-detection test generation.
ACM Great Lakes Symposium on VLSI 2009: 93-98 |
| 369 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality.
VLSI Design 2009: 215-220 |
| 368 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(1): 121-129 (2009) |
| 367 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 426-432 (2009) |
| 2008 |
|---|
| 366 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Circuit lines for guiding the generation of random test sequences for synchronous sequential circuits.
ASP-DAC 2008: 641-646 |
| 365 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Test vector chains for increased targeted and untargeted fault coverage.
ASP-DAC 2008: 663-666 |
| 364 | EE | Sudhakar M. Reddy,
Irith Pomeranz,
Chen Liu:
On tests to detect via opens in digital CMOS circuits.
DAC 2008: 840-845 |
| 363 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy.
DATE 2008: 1166-1171 |
| 362 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution.
DATE 2008: 1474-1479 |
| 361 | EE | Ilia Polian,
Sudhakar M. Reddy,
Irith Pomeranz,
Xun Tang,
Bernd Becker:
On Reducing Circuit Malfunctions Caused by Soft Errors.
DFT 2008: 245-253 |
| 360 | EE | Santiago Remersaro,
Janusz Rajski,
Thomas Rinderknecht,
Sudhakar M. Reddy,
Irith Pomeranz:
ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction.
DFT 2008: 385-393 |
| 359 | EE | Fan Yang,
Sreejit Chakravarty,
Narendra Devta-Prasanna,
Sudhakar M. Reddy,
Irith Pomeranz:
Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells.
DFT 2008: 394-402 |
| 358 | EE | Irith Pomeranz,
Sudhakar M. Reddy,
Sandip Kundu:
On Common-Mode Skewed-Load and Broadside Tests.
VLSI Design 2008: 151-156 |
| 357 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths.
VLSI Design 2008: 175-180 |
| 356 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity.
VLSI Design 2008: 181-186 |
| 355 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Synthesis for Broadside Testability of Transition Faults.
VTS 2008: 221-226 |
| 354 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests.
VTS 2008: 317-322 |
| 353 | EE | Fan Yang,
Sreejit Chakravarty,
Narendra Devta-Prasanna,
Sudhakar M. Reddy,
Irith Pomeranz:
On the Detectability of Scan Chain Internal Faults — An Industrial Case Study.
VTS 2008: 79-84 |
| 352 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects.
IEEE Trans. VLSI Syst. 16(1): 98-107 (2008) |
| 351 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion.
IEEE Trans. VLSI Syst. 16(7): 931-936 (2008) |
| 350 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 137-146 (2008) |
| 349 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 193-197 (2008) |
| 348 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 398-403 (2008) |
| 347 | EE | Hangkyu Lee,
Irith Pomeranz,
Sudhakar M. Reddy:
On Complete Functional Broadside Tests for Transition Faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 583-587 (2008) |
| 346 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On the Saturation of n-Detection Test Generation by Different Definitions With Increased n.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 946-957 (2008) |
| 2007 |
|---|
| 345 | EE | Zhuo Zhang,
Sudhakar M. Reddy,
Irith Pomeranz:
Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes.
ASP-DAC 2007: 817-822 |
| 344 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On test generation by input cube avoidance.
DATE 2007: 522-527 |
| 343 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
A-Diagnosis: A Complement to Z-Diagnosis.
DFT 2007: 235-242 |
| 342 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits.
DFT 2007: 457-455 |
| 341 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Diagnostic Test Generation Based on Subsets of Faults.
European Test Symposium 2007: 151-158 |
| 340 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault Diagnosis.
VLSI Design 2007: 498-503 |
| 339 | EE | Santiago Remersaro,
Xijiang Lin,
Sudhakar M. Reddy,
Irith Pomeranz,
Janusz Rajski:
Low Shift and Capture Power Scan Tests.
VLSI Design 2007: 793-798 |
| 338 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Functional Broadside Tests with Different Levels of Reachability.
VLSI Design 2007: 799-804 |
| 337 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs.
VTS 2007: 416-421 |
| 336 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Forming N-detection test sets without test generation.
ACM Trans. Design Autom. Electr. Syst. 12(2): (2007) |
| 335 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits
CoRR abs/0710.4637: (2007) |
| 334 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Worst-Case and Average-Case Analysis of n-Detection Test Sets
CoRR abs/0710.4735: (2007) |
| 333 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential Circuits.
Electr. Notes Theor. Comput. Sci. 174(4): 83-93 (2007) |
| 332 | EE | Santiago Remersaro,
Xijiang Lin,
Sudhakar M. Reddy,
Irith Pomeranz,
Janusz Rajski:
Scan-Based Tests with Low Switching Activity.
IEEE Design & Test of Computers 24(3): 268-275 (2007) |
| 331 | EE | Irith Pomeranz:
Invariant States and Redundant Logic in Synchronous Sequential Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(6): 1171-1175 (2007) |
| 330 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Generation of Broadside Transition-Fault Test Sets That Detect Four-Way Bridging Faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1311-1319 (2007) |
| 329 | EE | Irith Pomeranz,
Sudhakar M. Reddy,
Srikanth Venkataraman:
z-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1700-1712 (2007) |
| 2006 |
|---|
| 328 | EE | Gang Chen,
Sudhakar M. Reddy,
Irith Pomeranz,
Janusz Rajski:
A test pattern ordering algorithm for diagnosis with truncated fail data.
DAC 2006: 399-404 |
| 327 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Test compaction for transition faults under transparent-scan.
DATE 2006: 1264-1269 |
| 326 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Generation of broadside transition fault test sets that detect four-way bridging faults.
DATE 2006: 907-912 |
| 325 | EE | Narendra Devta-Prasanna,
Arun Gunda,
P. Krishnamurthy,
Sudhakar M. Reddy,
Irith Pomeranz:
Test Generation for Open Defects in CMOS Circuits.
DFT 2006: 41-49 |
| 324 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Scan-Based Delay Fault Tests for Diagnosis of Transition Faults.
DFT 2006: 419-427 |
| 323 | EE | Hangkyu Lee,
Suriyaprakash Natarajan,
Srinivas Patil,
Irith Pomeranz:
Selecting High-Quality Delay Tests for Manufacturing Test and Debug.
DFT 2006: 59-70 |
| 322 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Fault Collapsing for Transition Faults Using Extended Transition Faults.
European Test Symposium 2006: 173-178 |
| 321 | EE | Narendra Devta-Prasanna,
Arun Gunda,
P. Krishnamurthy,
Sudhakar M. Reddy,
Irith Pomeranz:
A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults.
European Test Symposium 2006: 185-192 |
| 320 | EE | Zhuo Zhang,
Sudhakar M. Reddy,
Irith Pomeranz,
Janusz Rajski,
Bashir M. Al-Hashimi:
Enhancing Delay Fault Coverage through Low Power Segmented Scan.
European Test Symposium 2006: 21-28 |
| 319 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
A delay fault model for at-speed fault simulation and test generation.
ICCAD 2006: 89-95 |
| 318 | EE | Chaowen Yu,
Sudhakar M. Reddy,
Irith Pomeranz:
A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BIST.
IOLTS 2006: 37-42 |
| 317 | EE | Gang Chen,
Sudhakar M. Reddy,
Irith Pomeranz,
Janusz Rajski:
New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic.
VLSI Design 2006: 419-424 |
| 316 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for Transition Faults.
VLSI Design 2006: 828-831 |
| 315 | EE | Hangkyu Lee,
Irith Pomeranz,
Sudhakar M. Reddy:
A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition Faults.
VTS 2006: 294-299 |
| 314 | EE | Zhuo Zhang,
Sudhakar M. Reddy,
Irith Pomeranz,
Xijiang Lin,
Janusz Rajski:
Scan Tests with Multiple Fault Activation Cycles for Delay Faults.
VTS 2006: 343-348 |
| 313 | EE | Bharath Seshadri,
Irith Pomeranz,
Srikanth Venkataraman,
Enamul Amyeen,
Sudhakar M. Reddy:
Dominance Based Analysis for Large Volume Production Fail Diagnosis.
VTS 2006: 392-399 |
| 312 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan.
IEEE Trans. Computers 55(4): 491-495 (2006) |
| 311 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Generation of Functional Broadside Tests for Transition Faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2207-2218 (2006) |
| 310 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Using Dummy Bridging Faults to Define Reduced Sets of Target Faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2219-2227 (2006) |
| 309 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Improved n-Detection Test Sequences Under Transparent Scan.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2492-2501 (2006) |
| 308 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Scan-BIST based on transition probabilities for circuits with single and multiple scan chains.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 591-596 (2006) |
| 307 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1170-1175 (2006) |
| 306 | EE | Yoshinobu Higami,
Seiji Kajihara,
Irith Pomeranz,
Shin-ya Kobayashi,
Yuzo Takamatsu:
On Finding Don't Cares in Test Sequences for Sequential Circuits.
IEICE Transactions 89-D(11): 2748-2755 (2006) |
| 2005 |
|---|
| 305 | EE | Chaowen Yu,
Sudhakar M. Reddy,
Irith Pomeranz:
Circuit Independent Weighted Pseudo-Random BIST Pattern Generator.
Asian Test Symposium 2005: 132-137 |
| 304 | EE | Narendra Devta-Prasanna,
Sudhakar M. Reddy,
Arun Gunda,
P. Krishnamurthy,
Irith Pomeranz:
Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions.
Asian Test Symposium 2005: 202-207 |
| 303 | EE | Irith Pomeranz:
N-detection under transparent-scan.
DAC 2005: 129-134 |
| 302 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits.
DATE 2005: 1008-1013 |
| 301 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Worst-Case and Average-Case Analysis of n-Detection Test Sets.
DATE 2005: 444-449 |
| 300 | EE | Huaxing Tang,
Gang Chen,
Sudhakar M. Reddy,
Chen Wang,
Janusz Rajski,
Irith Pomeranz:
Defect Aware Test Patterns.
DATE 2005: 450-455 |
| 299 | EE | Zhuo Zhang,
Sudhakar M. Reddy,
Irith Pomeranz:
On Generating Pseudo-Functional Delay Fault Tests for Scan Designs.
DFT 2005: 398-405 |
| 298 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Recovery During Concurrent On-Line Testing of Identical Circuits.
DFT 2005: 475-483 |
| 297 | EE | Narendra Devta-Prasanna,
Arun Gunda,
P. Krishnamurthy,
Sudhakar M. Reddy,
Irith Pomeranz:
A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals.
ICCD 2005: 471-474 |
| 296 | EE | Yuan Cai,
Sudhakar M. Reddy,
Irith Pomeranz,
Bashir M. Al-Hashimi:
Battery-aware dynamic voltage scaling in multiprocessor embedded system.
ISCAS (1) 2005: 616-619 |
| 295 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Dynamic Test Compaction for Bridging Faults.
ISQED 2005: 250-255 |
| 294 | EE | Wei Li,
Sudhakar M. Reddy,
Irith Pomeranz:
On Reducing Peak Current and Power during Test.
ISVLSI 2005: 156-161 |
| 293 | EE | Irith Pomeranz,
Srikanth Venkataraman,
Sudhakar M. Reddy:
Fault Diagnosis and Fault Model Aliasing.
ISVLSI 2005: 206-211 |
| 292 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Tuple Detection for Path Delay Faults: A Method for Improving Test Set Quality.
VLSI Design 2005: 41-46 |
| 291 | EE | Huaxing Tang,
Chen Wang,
Janusz Rajski,
Sudhakar M. Reddy,
Jerzy Tyszer,
Irith Pomeranz:
On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios.
VLSI Design 2005: 59-64 |
| 290 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Concurrent Online Testing of Identical Circuits Using Nonidentical Input Vectors.
IEEE Trans. Dependable Sec. Comput. 2(3): 190-200 (2005) |
| 289 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Autoscan: a scan design without external scan inputs or outputs.
IEEE Trans. VLSI Syst. 13(9): 1087-1095 (2005) |
| 288 | EE | Yonsang Cho,
Irith Pomeranz,
Sudhakar M. Reddy:
On reducing test application time for scan circuits using limited scan operations and transfer sequences.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1594-1605 (2005) |
| 287 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On masking of redundant faults in synchronous sequential circuits with design-for-testability logic.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 288-294 (2005) |
| 286 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On fault equivalence, fault dominance, and incompletely specified test sets.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(8): 1271-1274 (2005) |
| 2004 |
|---|
| 285 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Properties of Maximally Dominating Faults.
Asian Test Symposium 2004: 106-111 |
| 284 | EE | Chaowen Yu,
Sudhakar M. Reddy,
Irith Pomeranz:
Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults.
Asian Test Symposium 2004: 178-183 |
| 283 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
A Postprocessing Procedure of Test Enrichment for Path Delay Faults.
Asian Test Symposium 2004: 448-453 |
| 282 | EE | Wei Li,
Sudhakar M. Reddy,
Irith Pomeranz:
On test generation for transition faults with minimized peak power dissipation.
DAC 2004: 504-509 |
| 281 | EE | Irith Pomeranz:
On the generation of scan-based test sets with reachable states for testing under functional operation conditions.
DAC 2004: 928-933 |
| 280 | EE | Irith Pomeranz:
Scan-BIST based on transition probabilities.
DAC 2004: 940-943 |
| 279 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Level of Similarity: A Metric for Fault Collapsing.
DATE 2004: 56-61 |
| 278 | EE | Irith Pomeranz,
Srikanth Venkataraman,
Sudhakar M. Reddy,
Bharath Seshadri:
Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis.
DATE 2004: 68-75 |
| 277 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal Lines.
DFT 2004: 183-190 |
| 276 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Concurrent On-Line Testing of Identical Circuits Through Output Comparison Using Non-Identical Input Vectors.
DFT 2004: 469-476 |
| 275 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan.
ICCD 2004: 82-84 |
| 274 | EE | Yonsang Cho,
Irith Pomeranz,
Sudhakar M. Reddy:
Test Application Time Reduction for Scan Circuits Using Limited Scan Operations.
ISQED 2004: 211-216 |
| 273 | EE | Hangkyu Lee,
Irith Pomeranz,
Sudhakar M. Reddy:
Scan BIST Targeting Transition Faults Using a Markov Source.
ISQED 2004: 497-502 |
| 272 | EE | Irith Pomeranz,
Srikanth Venkataraman,
Sudhakar M. Reddy:
Z-DFD: Design-for-Diagnosability Based on the Concept of Z-Detection.
ITC 2004: 489-497 |
| 271 | EE | Irith Pomeranz,
Srikanth Venkataraman,
Sudhakar M. Reddy,
Enamul Amyeen:
Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults.
VLSI Design 2004: 475-480 |
| 270 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On Interconnecting Circuits with Multiple Scan Chains for Improved Test Data Compression.
VLSI Design 2004: 741-744 |
| 269 | EE | Irith Pomeranz,
Sandip Kundu,
Sudhakar M. Reddy:
Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units.
IEEE Trans. Computers 53(1): 83-88 (2004) |
| 268 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
A Measure of Quality for n-Detection Test Sets.
IEEE Trans. Computers 53(11): 1497-1503 (2004) |
| 267 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests.
IEEE Trans. Computers 53(12): 1569-1581 (2004) |
| 266 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit.
IEEE Trans. Computers 53(9): 1121-1133 (2004) |
| 265 | EE | Irith Pomeranz,
Yervant Zorian:
Fault isolation for nonisolated blocks.
IEEE Trans. VLSI Syst. 12(12): 1385-1388 (2004) |
| 264 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations.
IEEE Trans. VLSI Syst. 12(7): 780-788 (2004) |
| 263 | EE | Irith Pomeranz:
Constrained test generation for embedded synchronous sequential circuits with serial-input access.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 164-172 (2004) |
| 262 | EE | Irith Pomeranz:
Reducing test-data volume using P-testable scan chains in circuits with multiple scan chains.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(10): 1465-1478 (2004) |
| 261 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Vector-restoration-based static compaction using random initial omission.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(11): 1587-1592 (2004) |
| 260 | EE | Irith Pomeranz,
Sudhakar M. Reddy,
Sandip Kundu:
On the characterization and efficient computation of hard-to-detect bridging faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1640-1649 (2004) |
| 2003 |
|---|
| 259 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Test Data Volume Reduction by Test Data Realignment.
Asian Test Symposium 2003: 434-439 |
| 258 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
A DFT Approach for Path Delay Faults in Interconnected Circuits.
Asian Test Symposium 2003: 72-77 |
| 257 | EE | Wei Li,
Chaowen Yu,
Sudhakar M. Reddy,
Irith Pomeranz:
A scan BIST generation method using a markov source and partial bit-fixing.
DAC 2003: 554-559 |
| 256 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On test data compression and n-detection test sets.
DAC 2003: 748-751 |
| 255 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
A New Approach to Test Generation and Test Compaction for Scan Circuits.
DATE 2003: 11000-11005 |
| 254 | EE | Irith Pomeranz,
Sudhakar M. Reddy,
Sandip Kundu:
On the Characterization of Hard-to-Detect Bridging Faults.
DATE 2003: 11012-11019 |
| 253 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Test Data Compression Based on Output Dependence.
DATE 2003: 11186-11187 |
| 252 | EE | Chen Wang,
Sudhakar M. Reddy,
Irith Pomeranz,
Janusz Rajski,
Jerzy Tyszer:
On Compacting Test Response Data Containing Unknown Values.
ICCAD 2003: 855-862 |
| 251 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic.
ICCAD 2003: 867-873 |
| 250 | EE | Gang Chen,
Sudhakar M. Reddy,
Irith Pomeranz:
Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits.
ICCD 2003: 36-41 |
| 249 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Static Test Compaction for Multiple Full-Scan Circuits.
ICCD 2003: 393-396 |
| 248 | EE | Yoshinobu Higami,
Shin-ya Kobayashi,
Yuzo Takamatsu,
Seiji Kajihara,
Irith Pomeranz:
A Method to Find Don't Care Values in Test Sequences for Sequential Circuits.
ICCD 2003: 397- |
| 247 | EE | Chaowen Yu,
Wei Li,
Sudhakar M. Reddy,
Irith Pomeranz:
An Improved Markov Source Design for Scan BIST.
IOLTS 2003: 106-110 |
| 246 | EE | Mohamed A. Gomaa,
Chad Scarbrough,
Irith Pomeranz,
T. N. Vijaykumar:
Transient-Fault Recovery for Chip Multiprocessors.
ISCA 2003: 98-109 |
| 245 | EE | Masao Naruse,
Irith Pomeranz,
Sudhakar M. Reddy,
Sandip Kundu:
On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding.
ITC 2003: 1060-1068 |
| 244 | EE | Huaxing Tang,
Sudhakar M. Reddy,
Irith Pomeranz:
On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs.
ITC 2003: 1079-1088 |
| 243 | EE | Irith Pomeranz:
Reducing Test Data Volume Using Random-Testable and Periodic-Testable Scan Chains in Circuits with Multiple Scan Chains.
ITC 2003: 441-450 |
| 242 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences.
VLSI Design 2003: 335-340 |
| 241 | EE | Ganesh Venkataraman,
Sudhakar M. Reddy,
Irith Pomeranz:
GALLOP: Genetic Algorithm based Low Power FSM Synthesis by Simultaneous Partitioning and State Assignment.
VLSI Design 2003: 533-538 |
| 240 | | Wei Zou,
C. N. Chu,
Sudhakar M. Reddy,
Irith Pomeranz:
Optimizing SOC Test Resources using Dual Sequences.
VLSI-SOC 2003: 180-185 |
| 239 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit.
VTS 2003: 173-178 |
| 238 | EE | Wei Zou,
Sudhakar M. Reddy,
Irith Pomeranz,
Yu Huang:
SOC Test Scheduling Using Simulated Annealing.
VTS 2003: 325-330 |
| 237 | EE | Xiaoming Yu,
Enamul Amyeen,
Srikanth Venkataraman,
Ruifeng Guo,
Irith Pomeranz:
Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation.
VTS 2003: 351-358 |
| 236 | EE | Irith Pomeranz,
Sudhakar M. Reddy,
Yervant Zorian:
A Test Interface for Built-In Test of Non-Isolated Scanned Cores.
VTS 2003: 371-378 |
| 235 | EE | Sudhakar M. Reddy,
Kohei Miyase,
Seiji Kajihara,
Irith Pomeranz:
On test data volume reduction for multiple scan chain designs.
ACM Trans. Design Autom. Electr. Syst. 8(4): 460-469 (2003) |
| 234 | EE | Mohamed A. Gomaa,
Chad Scarbrough,
T. N. Vijaykumar,
Irith Pomeranz:
Transient-Fault Recovery for Chip Multiprocessors.
IEEE Micro 23(6): 76-83 (2003) |
| 233 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Test enrichment for path delay faults using multiple sets of target faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 82-90 (2003) |
| 232 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Test data compression based on input-output dependence.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1450-1455 (2003) |
| 231 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(12): 1663-1670 (2003) |
| 230 | EE | Ruifeng Guo,
Sudhakar M. Reddy,
Irith Pomeranz:
Reverse-order-restoration-based static test compaction for synchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 293-304 (2003) |
| 229 | EE | Enamul Amyeen,
W. Kent Fuchs,
Irith Pomeranz,
Vamsi Boppana:
Fault equivalence identification in combinational circuits using implication and evaluation techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(7): 922-936 (2003) |
| 228 | EE | Ruifeng Guo,
Sudhakar M. Reddy,
Irith Pomeranz:
PROPTEST: a property-based test generator for synchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 1080-1091 (2003) |
| 227 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Theorems for identifying undetectable faults in partial-scan circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 1092-1097 (2003) |
| 226 | EE | Yun Shao,
Sudhakar M. Reddy,
Irith Pomeranz,
Seiji Kajihara:
On Selecting Testable Paths in Scan Designs.
J. Electronic Testing 19(4): 447-456 (2003) |
| 225 | EE | Nadir Z. Basturkmen,
Sudhakar M. Reddy,
Irith Pomeranz:
A Low Power Pseudo-Random BIST Technique.
J. Electronic Testing 19(6): 637-644 (2003) |
| 2002 |
|---|
| 224 | EE | Yun Shao,
Irith Pomeranz,
Sudhakar M. Reddy:
On Generating High Quality Tests for Transition Faults.
Asian Test Symposium 2002: 1 |
| 223 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Delay Faults in Scan Circuits.
Asian Test Symposium 2002: 110-115 |
| 222 | EE | Ilia Polian,
Irith Pomeranz,
Bernd Becker:
Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests.
Asian Test Symposium 2002: 2-14 |
| 221 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test Sequences.
Asian Test Symposium 2002: 61-66 |
| 220 | EE | Seiji Kajihara,
Kenjiro Taniguchi,
Kohei Miyase,
Irith Pomeranz,
Sudhakar M. Reddy:
Test Data Compression Using Don?t-Care Identification and Statistical Encoding.
Asian Test Symposium 2002: 67- |
| 219 | EE | Irith Pomeranz,
Sandip Kundu,
Sudhakar M. Reddy:
On output response compression in the presence of unknown output values.
DAC 2002: 255-258 |
| 218 | EE | Irith Pomeranz,
Janusz Rajski,
Sudhakar M. Reddy:
Finding a Common Fault Response for Diagnosis during Silicon Debug.
DATE 2002: 1116 |
| 217 | EE | Irith Pomeranz,
Yervant Zorian:
Fault Isolation Using Tests for Non-Isolated Blocks.
DATE 2002: 1123 |
| 216 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults.
DATE 2002: 722-729 |
| 215 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Properties of Output Sequences and their Use in Guiding Property-Based Test Generation for Synchronous Sequential Circuits.
DELTA 2002: 377-381 |
| 214 | EE | Seiji Kajihara,
Kenjiro Taniguchi,
Irith Pomeranz,
Sudhakar M. Reddy:
Test Data Compression Using Don't-Care Identification and Statistical Encoding.
DELTA 2002: 413-416 |
| 213 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On undetectable faults in partial scan circuits.
ICCAD 2002: 82-86 |
| 212 | EE | Chen Wang,
Sudhakar M. Reddy,
Irith Pomeranz,
Xijiang Lin,
Janusz Rajski:
Conflict driven techniques for improving deterministic test pattern generation.
ICCAD 2002: 87-93 |
| 211 | EE | Kohei Miyase,
Seiji Kajihara,
Irith Pomeranz,
Sudhakar M. Reddy:
Don't-Care Identification on Specific Bits of Test Patterns.
ICCD 2002: 194-199 |
| 210 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On the Coverage of Delay Faults in Scan Designs with Multiple Scan Chains.
ICCD 2002: 206-209 |
| 209 | EE | Nadir Z. Basturkmen,
Sudhakar M. Reddy,
Irith Pomeranz:
A Low Power Pseudo-Random BIST Technique.
ICCD 2002: 468-473 |
| 208 | EE | Nadir Z. Basturkmen,
Sudhakar M. Reddy,
Irith Pomeranz:
A Low Power Pseudo-Random BIST Technique.
IOLTW 2002: 140- |
| 207 | EE | T. N. Vijaykumar,
Irith Pomeranz,
Karl Cheng:
Transient-Fault Recovery Using Simultaneous Multithreading.
ISCA 2002: 87-98 |
| 206 | EE | Nadir Z. Basturkmen,
Sudhakar M. Reddy,
Irith Pomeranz:
Pseudo Random Patterns Using Markov Sources for Scan BIST.
ITC 2002: 1013-1021 |
| 205 | EE | Sudhakar M. Reddy,
Irith Pomeranz,
Huaxing Tang,
Seiji Kajihara,
Kozo Kinoshita:
On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout.
ITC 2002: 83-89 |
| 204 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits.
VLSI Design 2002: 677-682 |
| 203 | EE | Yun Shao,
Irith Pomeranz,
Sudhakar M. Reddy:
Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples.
VLSI Design 2002: 767-772 |
| 202 | EE | Sudhakar M. Reddy,
Kohei Miyase,
Seiji Kajihara,
Irith Pomeranz:
On Test Data Volume Reduction for Multiple Scan Chain Designs.
VTS 2002: 103-110 |
| 201 | EE | Enamul Amyeen,
Irith Pomeranz,
W. Kent Fuchs:
Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits.
VTS 2002: 181-186 |
| 200 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set.
IEEE Trans. Computers 51(11): 1282-1293 (2002) |
| 199 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times.
IEEE Trans. Computers 51(4): 409-419 (2002) |
| 198 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector Omission.
IEEE Trans. Computers 51(7): 866-872 (2002) |
| 197 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 628-637 (2002) |
| 196 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(6): 706-714 (2002) |
| 195 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
n-pass n-detection fault simulation and its applications.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(8): 980-986 (2002) |
| 194 | EE | Irith Pomeranz:
On the use of random limited-scan to improve at-speed randompattern testing of scan circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1068-1076 (2002) |
| 2001 |
|---|
| 193 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
ITEM: an iterative improvement test generation procedure for synchronous sequential circuits.
ACM Great Lakes Symposium on VLSI 2001: 13-18 |
| 192 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
A Postprocessing Procedure to Reduce the Number of Different Test Lengths in a Test Set for Scan Circuits.
Asian Test Symposium 2001: 131-136 |
| 191 | EE | Yun Shao,
Sudhakar M. Reddy,
Seiji Kajihara,
Irith Pomeranz:
An Efficient Method to Identify Untestable Path Delay Faults.
Asian Test Symposium 2001: 233-238 |
| 190 | EE | Irith Pomeranz,
Sudhakar M. Reddy,
Xijiang Lin:
Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan.
Asian Test Symposium 2001: 467 |
| 189 | EE | Irith Pomeranz:
On Pass/Fail Dictionaries for Scan Circuits .
Asian Test Symposium 2001: 51-56 |
| 188 | EE | Ruifeng Guo,
Sudhakar M. Reddy,
Irith Pomeranz:
On Improving a Fault Simulation Based Test Generator for Synchronous Sequential Circuits.
Asian Test Symposium 2001: 82- |
| 187 | EE | Irith Pomeranz:
Random Limited-Scan to Improve Random Pattern Testing of Scan Circuits.
DAC 2001: 145-150 |
| 186 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
An Approach to Test Compaction for Scan Circuits that Enhances At-Speed Testing.
DAC 2001: 156-161 |
| 185 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Sequence reordering to improve the levels of compaction achievable by static compaction procedures.
DATE 2001: 214-218 |
| 184 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage.
DATE 2001: 504-508 |
| 183 | EE | Chen Wang,
Irith Pomeranz,
Sudhakar M. Reddy:
REDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits.
ICCAD 2001: 370-374 |
| 182 | | Irith Pomeranz,
Sudhakar M. Reddy:
COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static Compaction.
ICCD 2001: 142-147 |
| 181 | | Irith Pomeranz,
Sudhakar M. Reddy:
A Partitioning and Storage Based Built-in Test Pattern Generation Method for Synchronous Sequential Circuits.
ICCD 2001: 148-153 |
| 180 | | Xijiang Lin,
Janusz Rajski,
Irith Pomeranz,
Sudhakar M. Reddy:
On static test compaction and test pattern ordering for scan designs.
ITC 2001: 1088-1097 |
| 179 | | Irith Pomeranz,
Sudhakar M. Reddy:
A method to enhance the fault coverage obtained by output response comparison of identical circuits.
ITC 2001: 196-203 |
| 178 | | Irith Pomeranz,
Sudhakar M. Reddy:
On improving the stuck-at fault coverage of functional test sequences by using limited-scan operations.
ITC 2001: 211-220 |
| 177 | EE | Ruifeng Guo,
Irith Pomeranz,
Sudhakar M. Reddy:
On Improving Static Test Compaction for Sequential Circuits.
VLSI Design 2001: 111-116 |
| 176 | EE | Enamul Amyeen,
W. Kent Fuchs,
Irith Pomeranz,
Vamsi Boppana:
Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction.
VTS 2001: 124-130 |
| 175 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On the Use of Fault Dominance in n-Detection Test Generation.
VTS 2001: 352-357 |
| 174 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
A built-in self-test method for diagnosis of synchronous sequential circuits.
IEEE Trans. VLSI Syst. 9(2): 290-296 (2001) |
| 173 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units.
IEEE Trans. VLSI Syst. 9(5): 679-689 (2001) |
| 172 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Forward-looking fault simulation for improved static compaction.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(10): 1262-1265 (2001) |
| 171 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Vector replacement to improve static-test compaction forsynchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 336-342 (2001) |
| 170 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On diagnosis and diagnostic test generation for pattern-dependenttransition faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 791-800 (2001) |
| 169 | EE | Irith Pomeranz,
Y. Zonan:
Testing of scan circuits containing nonisolated random-logic legacycores.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(8): 980-993 (2001) |
| 2000 |
|---|
| 168 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On the feasibility of fault simulation using partial circuit descriptions.
Asian Test Symposium 2000: 108-113 |
| 167 | EE | Seiji Kajihara,
Takashi Shimono,
Irith Pomeranz,
Sudhakar M. Reddy:
Enhanced untestable path analysis using edge graphs.
Asian Test Symposium 2000: 139-144 |
| 166 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Reducing test application time for full scan circuits by the addition of transfer sequences.
Asian Test Symposium 2000: 317-322 |
| 165 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On diagnosis of pattern-dependent delay faults.
DAC 2000: 59-62 |
| 164 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits.
DATE 2000: 298-304 |
| 163 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Functional Test Generation for Full Scan Circuits.
DATE 2000: 396- |
| 162 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Test-Point Insertion to Enhance Test Compaction for Scan Designs.
DSN 2000: 375-381 |
| 161 | | Yu Huang,
Irith Pomeranz,
Sudhakar M. Reddy,
Janusz Rajski:
Improving the Proportion of At-Speed Tests in Scan BIST.
ICCAD 2000: 459-463 |
| 160 | | Irith Pomeranz,
Sudhakar M. Reddy:
Simulation Based Test Generation for Scan Designs.
ICCAD 2000: 544-549 |
| 159 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation.
ICCD 2000: 389-394 |
| 158 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs.
ICCD 2000: 395- |
| 157 | | Sudhakar M. Reddy,
Irith Pomeranz,
Seiji Kajihara,
Atsushi Murakami,
Sadami Takeoka,
Mitsuyasu Ohta:
On validating data hold times for flip-flops in sequential circuits.
ITC 2000: 317-325 |
| 156 | | Atsushi Murakami,
Seiji Kajihara,
Tsutomu Sasao,
Irith Pomeranz,
Sudhakar M. Reddy:
Selection of potentially testable path delay faults for test generation.
ITC 2000: 376-384 |
| 155 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Fault diagnosis based on parameters of output responses.
PRDC 2000: 139-147 |
| 154 | EE | Hideyuki Ichihara,
Kozo Kinoshita,
Irith Pomeranz,
Sudhakar M. Reddy:
Test Transformation to Improve Compaction by Statistical Encoding.
VLSI Design 2000: 294-299 |
| 153 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On Synchronizing Sequences and Unspecified Values in Output Responses of Synchronous Sequential Circuits.
VLSI Design 2000: 392-397 |
| 152 | EE | Xijiang Lin,
Wu-Tung Cheng,
Irith Pomeranz,
Sudhakar M. Reddy:
SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration.
VTS 2000: 205-212 |
| 151 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On Finding a Minimal Functional Description of a Finite-State Machine for Test Generation for Adjacent Machines.
IEEE Trans. Computers 49(1): 88-94 (2000) |
| 150 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits.
IEEE Trans. Computers 49(2): 175-181 (2000) |
| 149 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits.
IEEE Trans. Computers 49(6): 596-607 (2000) |
| 148 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On n-detection test sets and variable n-detection test sets fortransition faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(3): 372-383 (2000) |
| 147 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 589-600 (2000) |
| 146 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On synchronizable circuits and their synchronizing sequences.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 1086-1092 (2000) |
| 145 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time.
J. Electronic Testing 16(5): 541-552 (2000) |
| 1999 |
|---|
| 144 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Vector-Based Functional Fault Models for Delay Faults.
Asian Test Symposium 1999: 41-46 |
| 143 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Pattern Sensitivity: A Property to Guide Test Generation for Combinational Circuits.
Asian Test Symposium 1999: 75-80 |
| 142 | EE | Ruifeng Guo,
Sudhakar M. Reddy,
Irith Pomeranz:
Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction.
DAC 1999: 653-659 |
| 141 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences.
DAC 1999: 754-759 |
| 140 | EE | Xijiang Lin,
Irith Pomeranz,
Sudhakar M. Reddy:
Full Scan Fault Coverage With Partial Scan.
DATE 1999: 468-472 |
| 139 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
PASTA: Partial Scan to Enhance Test Compaction.
Great Lakes Symposium on VLSI 1999: 4-7 |
| 138 | EE | Xijiang Lin,
Irith Pomeranz,
Sudhakar M. Reddy:
Techniques for improving the efficiency of sequential circuit test generation.
ICCAD 1999: 147-151 |
| 137 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
An approach for improving the levels of compaction achieved by vector omission.
ICCAD 1999: 463-466 |
| 136 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits.
ICCD 1999: 412-417 |
| 135 | | Yun Shao,
Ruifeng Guo,
Sudhakar M. Reddy,
Irith Pomeranz:
The effects of test compaction on fault diagnosis.
ITC 1999: 1083-1089 |
| 134 | | Irith Pomeranz,
Sudhakar M. Reddy:
On achieving complete coverage of delay faults in full scan circuits using locally available lines.
ITC 1999: 923-931 |
| 133 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits.
VLSI Design 1999: 250-255 |
| 132 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
A Flexible Path Selection Procedure for Path Delay Fault Testing.
VTS 1999: 152-159 |
| 131 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults.
VTS 1999: 173-181 |
| 130 | EE | Enamul Amyeen,
W. Kent Fuchs,
Irith Pomeranz,
Vamsi Boppana:
Implication and Evaluation Techniques for Proving Fault Equivalence.
VTS 1999: 201-213 |
| 129 | EE | Ruifeng Guo,
Irith Pomeranz,
Sudhakar M. Reddy:
A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits.
VTS 1999: 260-267 |
| 128 | EE | Sudhakar M. Reddy,
Irith Pomeranz,
Nadir Z. Basturkmen,
Xijiang Lin:
Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits.
VTS 1999: 275-283 |
| 127 | EE | Irith Pomeranz,
Yervant Zorian:
Testing of Non-Isolated Embedded Legacy Cores and their Surrounding Logic.
VTS 1999: 41-48 |
| 126 | | Irith Pomeranz,
Sudhakar M. Reddy:
A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n-Detections in Combinational Circuits.
IEEE Trans. Computers 48(10): 1145-1152 (1999) |
| 125 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
A comment on "Improving a nonenumerative method to estimate path delay fault coverage".
IEEE Trans. on CAD of Integrated Circuits and Systems 18(5): 665-666 (1999) |
| 124 | EE | Irith Pomeranz,
Sudhakar M. Reddy,
Ruifeng Guo:
Static test compaction for synchronous sequential circuits based on vector restoration.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(7): 1040-1049 (1999) |
| 1998 |
|---|
| 123 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time.
Asian Test Symposium 1998: 198-203 |
| 122 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Test Generation for Synchronous Sequential Circuits to Reduce Storage Requirements.
Asian Test Symposium 1998: 446-451 |
| 121 | EE | Ruifeng Guo,
Irith Pomeranz,
Sudhakar M. Reddy:
On Speeding-Up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits .
Asian Test Symposium 1998: 467-471 |
| 120 | EE | Irith Pomeranz,
W. Kent Fuchs:
A Diagnostic Test Generation Procedure for Combinational Circuits Based on Test Elimination.
Asian Test Symposium 1998: 486-491 |
| 119 | EE | Ruifeng Guo,
Irith Pomeranz,
Sudhakar M. Reddy:
Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration.
DATE 1998: 583- |
| 118 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
A Synthesis Procedure for Flexible Logic Functions.
DATE 1998: 973-974 |
| 117 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines.
DATE 1998: 983-984 |
| 116 | | Irith Pomeranz,
Sudhakar M. Reddy:
A Generalized Test Generation Procedure for Path Delay Faults.
FTCS 1998: 274-283 |
| 115 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling.
Great Lakes Symposium on VLSI 1998: 216-221 |
| 114 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
A diagnostic test generation procedure for synchronous sequential circuits based on test elimination.
ITC 1998: 1074-1083 |
| 113 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On Test Compaction Objectives for Combinational and Sequential Circuits.
VLSI Design 1998: 279-284 |
| 112 | EE | Xijiang Lin,
Irith Pomeranz,
Sudhakar M. Reddy:
MIX: A Test Generation System for Synchronous Sequential Circuits.
VLSI Design 1998: 456-463 |
| 111 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On Synchronizing Sequences and Test Sequence Partitioning.
VTS 1998: 158-167 |
| 110 | EE | Xijiang Lin,
Irith Pomeranz,
Sudhakar M. Reddy:
On Removing Redundant Faults in Synchronous Sequential Circuits.
VTS 1998: 168-175 |
| 109 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage.
VTS 1998: 289-295 |
| 108 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Functional test generation for delay faults in combinational circuits.
ACM Trans. Design Autom. Electr. Syst. 3(2): 231-248 (1998) |
| 107 | | Irith Pomeranz,
Sudhakar M. Reddy:
Location of Stuck-At Faults and Bridging Faults Based on Circuit Partitioning.
IEEE Trans. Computers 47(10): 1124-1135 (1998) |
| 106 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On methods to match a test pattern generator to a circuit-under-test.
IEEE Trans. VLSI Syst. 6(3): 432-444 (1998) |
| 105 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Test sequences to achieve high defect coverage for synchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 1017-1029 (1998) |
| 104 | EE | Vinay Dabholkar,
Sreejit Chakravarty,
Irith Pomeranz,
Sudhakar M. Reddy:
Techniques for minimizing power dissipation in scan and combinational circuits during test application.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(12): 1325-1333 (1998) |
| 103 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Low-complexity fault simulation under the multiple observation time and the restricted multiple observation time testing approaches.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(3): 269-278 (1998) |
| 102 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Design-for-testability for path delay faults in large combinational circuits using test points.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(4): 333-343 (1998) |
| 101 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Delay fault models for VLSI circuits1.
Integration 26(1-2): 21-40 (1998) |
| 1997 |
|---|
| 100 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On the Compaction of Test Sets Produced by Genetic Optimization.
Asian Test Symposium 1997: 4-9 |
| 99 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
TEMPLATES: A Test Generation Procedure for Synchronous Sequential Circuits.
Asian Test Symposium 1997: 74- |
| 98 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Fault Simulation under the Multiple Observation Time Approach using Backward Implications.
DAC 1997: 608-613 |
| 97 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On improving genetic optimization based test generation.
ED&TC 1997: 506-511 |
| 96 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On the use of reset to increase the testability of interconnected finite-state machines.
ED&TC 1997: 554-559 |
| 95 | | Irith Pomeranz,
Sudhakar M. Reddy:
ACTIV-LOCSTEP: A Test Generation Procedure Based on Logic Simulation and Fault Activation.
FTCS 1997: 144-151 |
| 94 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On Generating Test Sets that Remain Valid in the Presence of Undetected Faults.
Great Lakes Symposium on VLSI 1997: 20-25 |
| 93 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Built-in test generation for synchronous sequential circuits.
ICCAD 1997: 421-426 |
| 92 | | Irith Pomeranz,
Sudhakar M. Reddy:
Vector Restoration Based Static Compaction of Test Sequences for Synchronous Sequential Circuits.
ICCD 1997: 360-365 |
| 91 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On the Detection of Reset Faults in Synchronous Sequential Circuits.
VLSI Design 1997: 470-474 |
| 90 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On Full Reset as a Design-For-Testability Technique.
VLSI Design 1997: 534-536 |
| 89 | EE | Seiji Kajihara,
Kozo Kinoshita,
Irith Pomeranz,
Sudhakar M. Reddy:
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths.
VLSI Design 1997: 82-87 |
| 88 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage.
VTS 1997: 329-335 |
| 87 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On n-detection test sequences for synchronous sequential circuits343.
VTS 1997: 336-343 |
| 86 | | Irith Pomeranz,
Sudhakar M. Reddy:
On Dictionary-Based Fault Location in Digital Logic Circuits.
IEEE Trans. Computers 46(1): 48-59 (1997) |
| 85 | | Irith Pomeranz,
Sudhakar M. Reddy:
Test Generation for Multiple State-Table Faults in Finite-State Machines.
IEEE Trans. Computers 46(7): 783-794 (1997) |
| 84 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On error correction in macro-based circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1088-1100 (1997) |
| 83 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
LOCSTEP: a logic-simulation-based test generation procedure.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(5): 544-554 (1997) |
| 82 | EE | Sudhakar M. Reddy,
Irith Pomeranz,
Seiji Kajihara:
Compact test sets for high defect coverage.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(8): 923-930 (1997) |
| 1996 |
|---|
| 81 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On Test Generation for Interconnected Finite-State Machines: The Input Sequence Propagation Problem.
Asian Test Symposium 1996: 16-21 |
| 80 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Low-Complexity Fault Diagnosis Under the Multiple Observation Time Testing Approach.
Asian Test Symposium 1996: 226-231 |
| 79 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On Static Compaction of Test Sequences for Synchronous Sequential Circuits.
DAC 1996: 215-220 |
| 78 | | Irith Pomeranz,
Sudhakar M. Reddy:
Dynamic Test Compaction for Synchronous Sequential Circuits using Static Compaction Techniques.
FTCS 1996: 53-61 |
| 77 | EE | Irith Pomeranz,
Sudhakar M. Reddy,
Janak H. Patel:
On Double Transition Faults as a Delay Fault Model.
Great Lakes Symposium on VLSI 1996: 282-287 |
| 76 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Fault Location based on Circuit Partitioning.
ICCD 1996: 154- |
| 75 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Fault Location Based on Circuit Partitioning.
ICCD 1996: 242-247 |
| 74 | | Elizabeth M. Rudnick,
Janak H. Patel,
Irith Pomeranz:
On Potential Fault Detection in Sequential Circuits.
ITC 1996: 142-149 |
| 73 | | Irith Pomeranz,
Sudhakar M. Reddy:
On Cancelling the Effects of Logic Sharing for Improved Path Delay Fault Testability.
ITC 1996: 357-366 |
| 72 | | Irith Pomeranz,
Nirmal R. Saxena,
Richard Reeve,
Paritosh Kulkarni,
Yan A. Li:
Generation of Test Cases for Hardware Design Verification of a Super-Scalar Fetch Processor.
ITC 1996: 904-913 |
| 71 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits.
VLSI Design 1996: 254-259 |
| 70 | EE | Prasanti Uppaluri,
Uwe Sparmann,
Irith Pomeranz:
On minimizing the number of test points needed to achieve complete robust path delay fault testability.
VTS 1996: 288-295 |
| 69 | EE | Sudhakar M. Reddy,
Irith Pomeranz,
Seiji Kajihara:
On the effects of test compaction on defect coverage.
VTS 1996: 430-437 |
| 68 | EE | Yuan Lu,
Irith Pomeranz:
Synchronization of large sequential circuits by partial reset.
VTS 1996: 93-98 |
| 67 | | Irith Pomeranz,
Sudhakar M. Reddy:
On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences.
IEEE Trans. Computers 45(1): 20-32 (1996) |
| 66 | | Irith Pomeranz,
Sudhakar M. Reddy:
On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits.
IEEE Trans. Computers 45(1): 50-62 (1996) |
| 1995 |
|---|
| 65 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Static compaction for two-pattern test sets.
Asian Test Symposium 1995: 222-228 |
| 64 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On Synthesis-for-Testability of Combinational Logic Circuits.
DAC 1995: 126-132 |
| 63 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On generating compact test sequences for synchronous sequential circuits.
EURO-DAC 1995: 105-110 |
| 62 | | Irith Pomeranz,
Sudhakar M. Reddy:
LOCSTEP: A Logic Simulation Based Test Generation Procedure.
FTCS 1995: 110-119 |
| 61 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Functional test generation for delay faults in combinational circuits.
ICCAD 1995: 687-694 |
| 60 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Test generation for multiple state-table faults in finite-state machines.
ICCD 1995: 292- |
| 59 | | Irith Pomeranz,
Sudhakar M. Reddy:
Low-Complexity Fault Simulation under the Multiplie Observation Time Testing Approach.
ITC 1995: 272-281 |
| 58 | EE | Sitaran Yadavalli,
Irith Pomeranz,
Sudhakar M. Reddy:
MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level.
VLSI Design 1995: 110-115 |
| 57 | EE | Remata S. Reddy,
Irith Pomeranz,
Sudhakar M. Reddy,
Seiji Kajihara:
Compact test generation for bridging faults under I/sub DDQ/ testing.
VTS 1995: 310-316 |
| 56 | | Irith Pomeranz,
Sudhakar M. Reddy:
Aliasing Computation Using Fault Simulation with Fault Dropping.
IEEE Trans. Computers 44(1): 139-144 (1995) |
| 55 | | Irith Pomeranz,
Sudhakar M. Reddy:
On Fault Simulation for Synchronous Sequential Circuits.
IEEE Trans. Computers 44(2): 335-340 (1995) |
| 54 | | Irith Pomeranz,
Sudhakar M. Reddy:
INCREDYBLE: A New Search Strategy for Design Automation Problems with Applications to Testing.
IEEE Trans. Computers 44(6): 792-804 (1995) |
| 53 | EE | Seiji Kajihara,
Irith Pomeranz,
Kozo Kinoshita,
Sudhakar M. Reddy:
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1496-1504 (1995) |
| 52 | EE | Irith Pomeranz,
Sudhakar M. Reddy,
Prasanti Uppaluri:
NEST: a nonenumerative test generation method for path delay faults in combinational circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1505-1515 (1995) |
| 51 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On correction of multiple design errors.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(2): 255-264 (1995) |
| 50 | EE | Tatiana Orenstein,
Zvi Kohavi,
Irith Pomeranz:
An optimal algorithm for cycle breaking in directed graphs.
J. Electronic Testing 7(1-2): 71-81 (1995) |
| 1994 |
|---|
| 49 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Design-for-Testability for Path Delay Faults in Large Combinatorial Circuits Using Test-Points.
DAC 1994: 358-364 |
| 48 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On Improving Fault Diagnosis for Synchronous Sequential Circuits.
DAC 1994: 504-509 |
| 47 | | Sudhakar M. Reddy,
Irith Pomeranz,
Rahul Jain:
On Codeword Testing of Two-Rail and Parity TSC Checkers.
FTCS 1994: 116-125 |
| 46 | | Prasanti Uppaluri,
Irith Pomeranz,
Sudhakar M. Reddy:
Test Pattern Generation for Path Delay Faults in Synchronous Sequential Circuits Using Multiple Fast Clocks and Multiple Observations Times.
FTCS 1994: 456-465 |
| 45 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On testing delay faults in macro-based combinational circuits.
ICCAD 1994: 332-339 |
| 44 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On error correction in macro-based circuits.
ICCAD 1994: 568-575 |
| 43 | | Irith Pomeranz,
Sudhakar M. Reddy:
On Achieving Complete Testability of Synchronous Sequential Circuits with Synchronizing Sequences.
ITC 1994: 1007-1016 |
| 42 | | Irith Pomeranz,
Sudhakar M. Reddy:
On Determining Symmetries in Inputs of Logic Circuits.
VLSI Design 1994: 255-260 |
| 41 | | Irith Pomeranz,
Sudhakar M. Reddy:
Application of Homing Sequences to Synchronous Sequential Circuit Testing.
IEEE Trans. Computers 43(5): 569-580 (1994) |
| 40 | | Irith Pomeranz,
Sudhakar M. Reddy:
On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation.
IEEE Trans. Computers 43(9): 1100-1105 (1994) |
| 39 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On determining symmetries in inputs of logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(11): 1428-1434 (1994) |
| 38 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(2): 240-250 (1994) |
| 37 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
SPADES-ACE: a simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(2): 251-263 (1994) |
| 36 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On achieving complete fault coverage for sequential machines.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(3): 378-386 (1994) |
| 1993 |
|---|
| 35 | EE | Seiji Kajihara,
Irith Pomeranz,
Kozo Kinoshita,
Sudhakar M. Reddy:
Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits.
DAC 1993: 102-106 |
| 34 | EE | Irith Pomeranz,
Sudhakar M. Reddy,
Prasanti Uppaluri:
NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits.
DAC 1993: 439-445 |
| 33 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
INCREDYBLE-TG: INCREmental DYnamic test generation based on LEarning.
DAC 1993: 80-85 |
| 32 | | Irith Pomeranz,
Sudhakar M. Reddy:
EXOP (Extended Operation): A New Logical Fault Model for Digital Circuits.
FTCS 1993: 166-175 |
| 31 | | Irith Pomeranz,
Sudhakar M. Reddy,
Janak H. Patel:
Theory and Practice of Sequential Machine Testing and Testability.
FTCS 1993: 330-337 |
| 30 | | Irith Pomeranz,
Sudhakar M. Reddy:
Design and Synthesis for Testability of Synchronous Sequential Circuits Based on Strong-Connectivity.
FTCS 1993: 492-501 |
| 29 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
Test generation for path delay faults based on learning.
ICCAD 1993: 428-435 |
| 28 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On diagnosis and correction of design errors.
ICCAD 1993: 500-507 |
| 27 | EE | Paul G. Ryan,
W. Kent Fuchs,
Irith Pomeranz:
Fault dictionary compression and equivalence class computation for sequential circuits.
ICCAD 1993: 508-511 |
| 26 | | Irith Pomeranz,
Sudhakar M. Reddy:
A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test.
ITC 1993: 998-1007 |
| 25 | | Irith Pomeranz,
Sudhakar M. Reddy:
On the Generation of Weights for Weighted Pseudo Random Testing.
VLSI Design 1993: 69-72 |
| 24 | | Irith Pomeranz,
Sudhakar M. Reddy:
Testing of Fault-Tolerant Hardware Through Partial Control of Inputs.
IEEE Trans. Computers 42(10): 1267-1271 (1993) |
| 23 | | Irith Pomeranz,
Sudhakar M. Reddy:
Classification of Faults in Synchronous Sequential Circuits.
IEEE Trans. Computers 42(9): 1066-1077 (1993) |
| 22 | EE | Irith Pomeranz,
Lakshmi N. Reddy,
Sudhakar M. Reddy:
COMPACTEST: a method to generate compact test sets for combinational circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 1040-1049 (1993) |
| 21 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 1050-1058 (1993) |
| 20 | EE | Irith Pomeranz,
Kwang-Ting Cheng:
STOIC: state assignment based on output/input functions.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1123-1131 (1993) |
| 1992 |
|---|
| 19 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
At-Speed Delay Testing of Synchronous Sequential Circuits.
DAC 1992: 177-181 |
| 18 | EE | Irith Pomeranz,
Kwang-Ting Cheng:
State Assignment Using Input/Output Functions.
DAC 1992: 573-577 |
| 17 | | Irith Pomeranz,
Sudhakar M. Reddy:
A Divide-And-Conquer Approach to Test Generation for Large Synchronous Sequential Circuits.
FTCS 1992: 230-237 |
| 16 | | Niraj K. Jha,
Irith Pomeranz,
Sudhakar M. Reddy,
Robert J. Miller:
Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability.
FTCS 1992: 280-287 |
| 15 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On the generation of small dictionaries for fault location.
ICCAD 1992: 272-279 |
| 14 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
An efficient non-enumerative method to estimate path delay fault coverage.
ICCAD 1992: 560-567 |
| 13 | EE | Lakshmi N. Reddy,
Irith Pomeranz,
Sudhakar M. Reddy:
COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits.
ICCAD 1992: 568-574 |
| 12 | | Venkataramana Kommu,
Irith Pomeranz:
Effect of Communication in a Parallel Genetic Algorithm.
ICPP (3) 1992: 310-317 |
| 11 | | Irith Pomeranz,
Sudhakar M. Reddy:
The Multiple Observation Time Test Strategy.
IEEE Trans. Computers 41(5): 627-637 (1992) |
| 10 | EE | Irith Pomeranz,
Zvi Kohavi:
A limited exponential complexity algorithm for increasing the testability of digital circuits by testing-module insertion.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(2): 247-259 (1992) |
| 1991 |
|---|
| 9 | EE | Irith Pomeranz,
Sudhakar M. Reddy:
On Achieving a Complete Fault Coverage for Sequential Machines Using the Transition Fault Model.
DAC 1991: 341-346 |
| 8 | | Irith Pomeranz,
Sudhakar M. Reddy:
Test Generation for Synchronous Sequential Circuits Using Multiple Observation Times.
FTCS 1991: 52-59 |
| 7 | | Irith Pomeranz,
Sudhakar M. Reddy:
Testing of Fault-Tolerant Hardware.
Fault-Tolerant Computing Systems 1991: 148-159 |
| 6 | | Irith Pomeranz,
Sudhakar M. Reddy:
Test Generation for Synchronous Sequential Circuits Based on Fault Extraction.
ICCAD 1991: 450-453 |
| 5 | | Irith Pomeranz,
Sudhakar M. Reddy,
Lakshmi N. Reddy:
Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test Strategy.
ICCAD 1991: 454-457 |
| 4 | | Irith Pomeranz,
Lakshmi N. Reddy,
Sudhakar M. Reddy:
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits.
ITC 1991: 194-203 |
| 3 | | Irith Pomeranz,
Sudhakar M. Reddy:
Achieving Complete Delay Fault Testability by Extra Inputs.
ITC 1991: 273-282 |
| 2 | | Irith Pomeranz,
Zvi Kohavi:
Polynomial Complexity Algorithms for Increasing the Testability of Digital Circuits by Testing Module Insertion.
IEEE Trans. Computers 40(11): 1198-1214 (1991) |
| 1 | EE | Irith Pomeranz,
Zvi Kohavi:
The minimum test set problem for circuits with nonreconvergent fanout.
J. Electronic Testing 2(4): 339-349 (1991) |
