| 2008 |
|---|
| 15 | EE | Seyed-Abdollah Aftabjahani,
Linda S. Milor:
Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis.
ISQED 2008: 148-151 |
| 14 | EE | Cheng Jia,
Linda S. Milor:
A BIST Circuit for DLL Fault Detection.
IEEE Trans. VLSI Syst. 16(12): 1687-1695 (2008) |
| 13 | EE | Munkang Choi,
Linda S. Milor:
Diagnosis of Optical Lithography Faults With Product Test Sets.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1657-1669 (2008) |
| 2006 |
|---|
| 12 | EE | Munkang Choi,
Linda S. Milor:
Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1350-1367 (2006) |
| 2005 |
|---|
| 11 | EE | Changsoo Hong,
Linda S. Milor,
Munkang Choi,
Tom Lin:
Study of Area Scaling Effect on Integrated Circuit Reliability Based on Yield Models.
Microelectronics Reliability 45(9-11): 1305-1310 (2005) |
| 2003 |
|---|
| 10 | EE | Cheng Jia,
Linda S. Milor:
A BIST Solution for The Test of I/O Speed.
ITC 2003: 1023-1030 |
| 2002 |
|---|
| 9 | EE | Michael Orshansky,
Linda Milor,
Pinhong Chen,
Kurt Keutzer,
Chenming Hu:
Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 544-553 (2002) |
| 2000 |
|---|
| 8 | | Michael Orshansky,
Linda Milor,
Pinhong Chen,
Kurt Keutzer,
Chenming Hu:
Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits.
ICCAD 2000: 62-67 |
| 1996 |
|---|
| 7 | EE | Mien Li,
Linda S. Milor:
Computing Parametric Yield Adaptively Using Local Linear Models.
DAC 1996: 831-836 |
| 6 | EE | Bozena Kaminska,
Tad A. Kwasniewski,
Linda S. Milor,
G. Roberts,
P. Flahive,
Jérôme Wojcik:
Is High Frequency Analog DFT Possible?
VTS 1996: 214-215 |
| 1994 |
|---|
| 5 | EE | Linda S. Milor,
Alberto L. Sangiovanni-Vincentelli:
Minimizing production test time to detect faults in analog circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(6): 796-813 (1994) |
| 1990 |
|---|
| 4 | | Linda Milor,
Alberto L. Sangiovanni-Vincentelli:
Computing Parametric Yield Accurately and Efficiently.
ICCAD 1990: 116-119 |
| 3 | | Linda Milor,
Alberto L. Sangiovanni-Vincentelli:
Optimal Test Set Design for Analog Circuits.
ICCAD 1990: 294-297 |
| 1989 |
|---|
| 2 | EE | Linda S. Milor,
V. Visvanathan:
Detection of catastrophic faults in analog integrated circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(2): 114-130 (1989) |
| 1986 |
|---|
| 1 | EE | V. Visvanathan,
Linda S. Milor:
An Efficient Algorithm to Determine the Image of a Parallelepiped Under a Linear Transformation.
Symposium on Computational Geometry 1986: 207-215 |
