| 2009 |
|---|
| 36 | EE | Shih-Hsu Huang,
Chia-Ming Chang,
Yow-Tyng Nieh:
Opposite-phase register switching for peak current minimization.
ACM Trans. Design Autom. Electr. Syst. 14(1): (2009) |
| 2008 |
|---|
| 35 | EE | Chia-Ming Chang,
Shih-Hsu Huang,
Yuan-Kai Ho,
Jia-Zong Lin,
Hsin-Po Wang,
Yu-Sheng Lu:
Type-matching clock tree for zero skew clock gating.
DAC 2008: 714-719 |
| 34 | EE | Shih-Hsu Huang,
Chun-Hua Cheng:
An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management.
IEICE Transactions 91-A(1): 375-382 (2008) |
| 33 | EE | Shih-Hsu Huang,
Chun-Hua Cheng:
Power-Management Scheduling for Peak Power Minimization.
J. Inf. Sci. Eng. 24(6): 1647-1668 (2008) |
| 2007 |
|---|
| 32 | EE | Shih-Hsu Huang,
Chun-Hua Cheng,
Chia-Ming Chang,
Yow-Tyng Nieh:
Clock Period Minimization with Minimum Delay Insertion.
DAC 2007: 970-975 |
| 31 | EE | Shih-Hsu Huang,
Chu-Liao Wang,
Man-Lin Huang:
A Floorplan-Based Power Network Analysis Methodology for System-on-Chip Designs.
EUC 2007: 507-516 |
| 30 | EE | Wei-Ting Yen,
Shih-Hsu Huang,
Chun-Hua Cheng:
Simultaneous Operation Scheduling and Operation Delay Selection to Minimize Cycle-by-Cycle Power Differential.
EUC Workshops 2007: 638-647 |
| 29 | EE | Shih-Hsu Huang,
Yow-Tyng Nieh:
Clock skew scheduling with race conditions considered.
ACM Trans. Design Autom. Electr. Syst. 12(4): (2007) |
| 28 | EE | Yow-Tyng Nieh,
Shih-Hsu Huang,
Sheng-Yu Hsu:
Opposite-Phase Clock Tree for Peak Current Reduction.
IEICE Transactions 90-A(12): 2727-2735 (2007) |
| 27 | EE | Shih-Hsu Huang,
Chia-Ming Chang,
Yow-Tyng Nieh:
A Fast Register Scheduling Approach to the Architecture of Multiple Clocking Domains.
J. Inf. Sci. Eng. 23(6): 1681-1705 (2007) |
| 2006 |
|---|
| 26 | EE | Shih-Hsu Huang,
Chun-Hua Cheng:
Operation Scheduling for False Loop Free Circuits.
APCCAS 2006: 1619-1622 |
| 25 | EE | Shih-Hsu Huang,
Chun-Hua Cheng,
Chung-Hsin Chiang,
Chia-Ming Chang:
Peak Power Minimization through Power Management Scheduling.
APCCAS 2006: 868-871 |
| 24 | EE | Shih-Hsu Huang,
Chia-Ming Chang,
Yow-Tyng Nieh:
Fast multi-domain clock skew scheduling for peak current reduction.
ASP-DAC 2006: 254-259 |
| 23 | EE | Shih-Hsu Huang,
Chun-Hua Cheng,
Yow-Tyng Nieh,
Wei-Chieh Yu:
Register binding for clock period minimization.
DAC 2006: 439-444 |
| 22 | EE | Shih-Hsu Huang,
Chia-Ming Chang,
Yow-Tyng Nieh:
State re-encoding for peak current minimization.
ICCAD 2006: 33-38 |
| 21 | EE | Shih-Hsu Huang,
Chun-Hua Cheng,
Chung-Hsin Chiang,
Chia-Ming Chang:
An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management.
JCIS 2006 |
| 20 | EE | Shih-Hsu Huang,
Shi-Zhi Liu,
Yi-Rung Chen,
Jian-Yuan Lai:
High-Speed Fuzzy Inference Processor Using Active Rules Identification.
JCIS 2006 |
| 19 | EE | Shih-Hsu Huang,
Yow-Tyng Nieh:
Synthesis of nonzero clock skew circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 961-976 (2006) |
| 18 | EE | Shih-Hsu Huang,
Chun-Hua Cheng:
An ILP Approach to the Slack Driven Scheduling Problem.
IEICE Transactions 89-A(6): 1852-1858 (2006) |
| 2005 |
|---|
| 17 | EE | Yow-Tyng Nieh,
Shih-Hsu Huang,
Sheng-Yu Hsu:
Minimizing peak current via opposite-phase clock tree.
DAC 2005: 182-185 |
| 16 | EE | Shih-Hsu Huang,
Yow-Tyng Nieh,
Feng-Pin Lu:
Race-condition-aware clock skew scheduling.
DAC 2005: 475-478 |
| 15 | EE | Shih-Hsu Huang,
Yi-Rung Chen:
VLSI implementation of type-2 fuzzy inference processor.
ISCAS (4) 2005: 3307-3310 |
| 14 | EE | Shih-Hsu Huang,
Chun-Hua Cheng:
A formal approach to the slack driven scheduling problem in high-level synthesis.
ISCAS (6) 2005: 5633-5636 |
| 13 | EE | Chih-Hung Lee,
Chin-Hung Su,
Shih-Hsu Huang,
Chih-Yuan Lin,
Tsai-Ming Hsieh:
Floorplanning with clock tree estimation.
ISCAS (6) 2005: 6244-6247 |
| 12 | EE | Shih-Hsu Huang,
Chung-Hsin Chiang,
Chun-Hua Cheng:
Three-dimension scheduling under multi-cycle interconnect communications.
IEICE Electronic Express 2(4): 108-114 (2005) |
| 11 | EE | Shih-Hsu Huang,
Jian-Yuan Lai:
A High Speed Fuzzy Inference Processor with Dynamic Analysis and Scheduling Capabilities.
IEICE Transactions 88-D(10): 2410-2416 (2005) |
| 10 | EE | Shih-Hsu Huang,
Jian-Yuan Lai:
High-Speed VLSI Fuzzy Inference Processor for Trapezoid-Shaped Membership Functions.
J. Inf. Sci. Eng. 21(3): 607-626 (2005) |
| 2003 |
|---|
| 9 | EE | Shih-Hsu Huang,
Yow-Tyng Nieh:
Clock Period Minimization of Non-Zero Clock Skew Circuits.
ICCAD 2003: 809-812 |
| 2002 |
|---|
| 8 | EE | Shih-Hsu Huang,
Yi-Siang Hsu:
A timing driven approach for crosstalk minimization in gridded channel routing.
APCCAS (1) 2002: 263-266 |
| 7 | EE | Shih-Hsu Huang,
Wen-Hon Peng,
Jian-Yuan Lai:
Automatic synthesis of fuzzy systems based on trapezoid-shaped membership functions.
APCCAS (2) 2002: 43-46 |
| 6 | EE | Shih-Hsu Huang,
Chu-Liao Wang:
An effective floorplan-based power distribution network design methodology under reliability constraints.
ISCAS (1) 2002: 353-356 |
| 2001 |
|---|
| 5 | | Shih-Hsu Huang,
Jian-Yuan Lai:
A High Speed VLSI Fuzzy Logic Controller With Pipeline Architecture.
FUZZ-IEEE 2001: 1054-1057 |
| 4 | EE | Shih-Hsu Huang:
An effective low power design methodology based on interconnect prediction.
SLIP 2001: 189-194 |
| 2000 |
|---|
| 3 | EE | Mely Chen Chi,
Shih-Hsu Huang:
A Reliable Clock Tree Design Methodology for ASIC Designs.
ISQED 2000: 269-274 |
| 1995 |
|---|
| 2 | EE | Shih-Hsu Huang,
Ta-Yung Liu,
Yu-Chin Hsu,
Yen-Jen Oyang:
Synthesis of false loop free circuits.
ASP-DAC 1995 |
| 1992 |
|---|
| 1 | EE | Shih-Hsu Huang,
Cheng-Tsung Hwang,
Yu-Chin Hsu,
Yen-Jen Oyang:
A new approach to schedule operations across nested-ifs and nested-loops.
MICRO 1992: 268-271 |
