2008 | ||
---|---|---|
68 | EE | Girish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones: Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip. ACM Great Lakes Symposium on VLSI 2008: 351-354 |
67 | EE | Girish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones: Variation-tolerant, low-power PN-code acquisition using stochastic sensor NOC. ISCAS 2008: 380-383 |
66 | EE | Rami A. Abdallah, Naresh R. Shanbhag: Error-resilient low-power Viterbi decoders. ISLPED 2008: 111-116 |
65 | EE | Girish Varatkar, Naresh R. Shanbhag: Error-Resilient Motion Estimation Architecture. IEEE Trans. VLSI Syst. 16(10): 1399-1412 (2008) |
64 | EE | Srinivasa R. Sridhara, Ganesh Balamurugan, Naresh R. Shanbhag: Joint Equalization and Coding for On-Chip Bus Communication. IEEE Trans. VLSI Syst. 16(3): 314-318 (2008) |
2007 | ||
63 | EE | Srinivasa R. Sridhara, Naresh R. Shanbhag: Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes. IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 977-982 (2007) |
2006 | ||
62 | EE | Girish Varatkar, Naresh R. Shanbhag: Energy-efficient motion estimation using error-tolerance. ISLPED 2006: 113-118 |
61 | EE | Ming Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, N. J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, S. J. Patel: Sequential Element Design With Built-In Soft Error Resilience. IEEE Trans. VLSI Syst. 14(12): 1368-1378 (2006) |
60 | EE | Byonghyo Shim, Naresh R. Shanbhag: Energy-efficient soft error-tolerant digital signal processing. IEEE Trans. VLSI Syst. 14(4): 336-348 (2006) |
59 | EE | Ming Zhang, Naresh R. Shanbhag: Soft-Error-Rate-Analysis (SERA) Methodology. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2140-2155 (2006) |
2005 | ||
58 | EE | Ming Zhang, Naresh R. Shanbhag: An energy-efficient circuit technique for single event transient noise-tolerance. ISCAS (1) 2005: 636-639 |
57 | EE | Srinivasa R. Sridhara, Naresh R. Shanbhag: A low-power bus design using joint repeater insertion and coding. ISLPED 2005: 99-102 |
56 | EE | Srinivasa R. Sridhara, Naresh R. Shanbhag, Ganesh Balamurugan: Joint Equalization and Coding for On-Chip Bus Communication. ISQED 2005: 642-647 |
55 | EE | Srinivasa R. Sridhara, Naresh R. Shanbhag: Coding for Reliable On-Chip Buses: Fundamental Limits and Practical Codes. VLSI Design 2005: 417-422 |
54 | EE | Srinivasa R. Sridhara, Naresh R. Shanbhag: Coding for system-on-chip networks: a unified framework. IEEE Trans. VLSI Syst. 13(6): 655-667 (2005) |
53 | EE | Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer: Area-efficient high-throughput MAP decoder architectures. IEEE Trans. VLSI Syst. 13(8): 921-933 (2005) |
52 | EE | Seok-Jun Lee, Andrew C. Singer, Naresh R. Shanbhag: Linear turbo equalization analysis via BER transfer and EXIT charts. IEEE Transactions on Signal Processing 53(8-1): 2883-2897 (2005) |
51 | EE | Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer: Energy Efficient VLSI Architecture for Linear Turbo Equalizer. VLSI Signal Processing 39(1-2): 49-62 (2005) |
50 | EE | Naresh R. Shanbhag, Keshab K. Parhi: Guest Editorial. VLSI Signal Processing 39(1-2): 5-6 (2005) |
49 | EE | Mohammad M. Mansour, Naresh R. Shanbhag: A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes. VLSI Signal Processing 40(3): 371-382 (2005) |
2004 | ||
48 | EE | Srinivasa R. Sridhara, Naresh R. Shanbhag: Coding for system-on-chip networks: a unified framework. DAC 2004: 103-106 |
47 | EE | Naresh R. Shanbhag: A communication-theoretic design paradigm for reliable SOCs. DAC 2004: 76 |
46 | EE | Ming Zhang, Naresh R. Shanbhag: A soft error rate analysis (SERA) methodology. ICCAD 2004: 111-118 |
45 | EE | Srinivasa R. Sridhara, Arshad Ahmed, Naresh R. Shanbhag: Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses. ICCD 2004: 12-17 |
44 | EE | Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer: Switching methods for linear turbo equalization. ISCAS (3) 2004: 601-604 |
43 | EE | Naresh R. Shanbhag: Reliable and Efficient System-on-Chip Design. IEEE Computer 37(3): 42-50 (2004) |
42 | Byonghyo Shim, Srinivasa R. Sridhara, Naresh R. Shanbhag: Reliable low-power digital signal processing via reduced precision redundancy. IEEE Trans. VLSI Syst. 12(5): 497-510 (2004) | |
2003 | ||
41 | EE | Ganesh Balamurugan, Naresh R. Shanbhag: Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links. ICCD 2003: 254-260 |
40 | EE | Hyeon-Min Bae, Naresh R. Shanbhag: High bandwidth transimpedance amplifier design using active transmission lines. ISCAS (1) 2003: 253-256 |
39 | EE | Mohammad M. Mansour, Naresh R. Shanbhag: Architecture-aware low-density parity-check codes. ISCAS (2) 2003: 57-60 |
38 | EE | Byonghyo Shim, Naresh R. Shanbhag: Performance analysis of algorithmic noise-tolerance techniques. ISCAS (4) 2003: 113-116 |
37 | EE | Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer: A low-power VLSI architecture for turbo decoding. ISLPED 2003: 366-371 |
36 | EE | Lei Wang, Naresh R. Shanbhag: Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise. IEEE Trans. VLSI Syst. 11(2): 254-269 (2003) |
35 | EE | Lei Wang, Naresh R. Shanbhag: Low-power MIMO signal processing. IEEE Trans. VLSI Syst. 11(3): 434-445 (2003) |
34 | EE | Mohammad M. Mansour, Naresh R. Shanbhag: VLSI architectures for SISO-APP decoders. IEEE Trans. VLSI Syst. 11(4): 627-650 (2003) |
33 | EE | Mohammad M. Mansour, Naresh R. Shanbhag: High-throughput LDPC decoders. IEEE Trans. VLSI Syst. 11(6): 976-996 (2003) |
2002 | ||
32 | EE | Naresh R. Shanbhag: Reliable and energy-efficient digital signal processing. DAC 2002: 830-835 |
31 | EE | Mohammad M. Mansour, Naresh R. Shanbhag: Simplified current and delay models for deep submicron CMOS digital circuits. ISCAS (5) 2002: 109-112 |
30 | EE | Mohammad M. Mansour, Naresh R. Shanbhag: Low-power VLSI decoder architectures for LDPC codes. ISLPED 2002: 284-289 |
2001 | ||
29 | EE | Lei Wang, Naresh R. Shanbhag: Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers. ISLPED 2001: 334-339 |
28 | EE | Dilip V. Sarwate, Naresh R. Shanbhag: High-speed architectures for Reed-Solomon decoders. IEEE Trans. VLSI Syst. 9(5): 641-655 (2001) |
27 | EE | Rajamohana Hegde, Naresh R. Shanbhag: Soft digital signal processing. IEEE Trans. VLSI Syst. 9(6): 813-823 (2001) |
26 | EE | Swaroop Appadwedula, Manish Goel, Naresh R. Shanbhag, Douglas L. Jones, Kannan Ramchandran: Total System Energy Minimization for Wireless Image Transmission. VLSI Signal Processing 27(1-2): 99-117 (2001) |
25 | EE | Wayne Burleson, Naresh R. Shanbhag: Guest Editorial: Reconfigurable Signal Processing Systems. VLSI Signal Processing 28(1-2): 5-6 (2001) |
2000 | ||
24 | Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang: Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. ICCAD 2000: 318-321 | |
23 | EE | Naresh R. Shanbhag, K. Soumyanath, Samuel Martin: Reliable low-power design in the presence of deep submicron noise (embedded tutorial session). ISLPED 2000: 295-302 |
22 | EE | Rajamohana Hegde, Naresh R. Shanbhag: Toward achieving energy efficiency in presence of deep submicron noise. IEEE Trans. VLSI Syst. 8(4): 379-391 (2000) |
1999 | ||
21 | EE | Lei Wang, Naresh R. Shanbhag: Noise-tolerant dynamic circuit design. ISCAS (1) 1999: 549-552 |
20 | EE | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: Low-power distributed arithmetic architectures using nonuniform memory partitioning. ISCAS (3) 1999: 470-473 |
19 | EE | Rajamohana Hegde, Naresh R. Shanbhag: Lower bounds on energy dissipation and noise-tolerance for deep submicron VLSI. ISCAS (6) 1999: 334-337 |
18 | EE | Ganesh Balamurugan, Naresh R. Shanbhag: Energy-efficient dynamic circuit design in the presence of crosstalk noise. ISLPED 1999: 24-29 |
17 | EE | Rajamohana Hegde, Naresh R. Shanbhag: Energy-efficient signal processing via algorithmic noise-tolerance. ISLPED 1999: 30-35 |
16 | EE | Sudhakar Bobba, Ibrahim N. Hajj, Naresh R. Shanbhag: Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures. VLSI Design 1999: 358- |
15 | EE | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: A coding framework for low-power address and data busses. IEEE Trans. VLSI Syst. 7(2): 212-221 (1999) |
14 | EE | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: Information-theoretic bounds on average signal transition activity [VLSI systems]. IEEE Trans. VLSI Syst. 7(3): 359-368 (1999) |
13 | EE | Manish Goel, Naresh R. Shanbhag: Dynamic algorithm transformations (DAT)-a systematic approach to low-power reconfigurable signal processing. IEEE Trans. VLSI Syst. 7(4): 463-476 (1999) |
1998 | ||
12 | EE | Rajamohana Hegde, Naresh R. Shanbhag: Energy-efficiency in presence of deep submicron noise. ICCAD 1998: 228-234 |
11 | EE | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: Decorrelating (DECOR) transformations for low-power adaptive filters. ISLPED 1998: 250-255 |
10 | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications. VLSI Design 1998: 18-23 | |
1997 | ||
9 | EE | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: Analytical Estimation of Transition Activity From Word-Level Signal Statistics. DAC 1997: 582-587 |
8 | EE | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: Achievable bounds on signal transition activity. ICCAD 1997: 126-129 |
7 | EE | Manish Goel, Naresh R. Shanbhag: Dynamic algorithm transformation (DAT) for low-power adaptive signal processing. ISLPED 1997: 161-166 |
6 | EE | Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: Analytical estimation of signal transition activity from word-level statistics. IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 718-733 (1997) |
1996 | ||
5 | EE | Manish Goel, Naresh R. Shanbhag: Low-power adaptive filter architectures via strength reduction. ISLPED 1996: 217-220 |
4 | EE | Naresh R. Shanbhag: Lower bounds on power dissipation for DSP algorithms. ISLPED 1996: 43-48 |
1995 | ||
3 | Naresh R. Shanbhag, Gi-Hong Im: Pipelined Adaptive IIR Filter Architecture. ISCAS 1995: 558-561 | |
1993 | ||
2 | Naresh R. Shanbhag, Keshab K. Parhi: A Pipelined Adaptive Differential Vector Quantizer for Low-power Speech Coding Applications. ISCAS 1993: 1956-1958 | |
1 | Naresh R. Shanbhag, Keshab K. Parhi: Roundoff error analysis of the pipelined ADPCM coder. ISCAS 1993: 886-889 |