| 2009 |
|---|
| 190 | EE | Hushrav Mogal,
Haifeng Qian,
Sachin S. Sapatnekar,
Kia Bazargan:
Fast and Accurate Statistical Criticality Computation Under Process Variations.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 350-363 (2009) |
| 2008 |
|---|
| 189 | EE | Sachin S. Sapatnekar,
Eshel Haritan,
Kurt Keutzer,
Anirudh Devgan,
Desmond Kirkpatrick,
Stephen Meier,
Duaine Pryor,
Tom Spyrou:
Reinventing EDA with manycore processors.
DAC 2008: 126-127 |
| 188 | EE | Ping-Hung Yuh,
Sachin S. Sapatnekar,
Chia-Lin Yang,
Yao-Wen Chang:
A progressive-ILP based routing algorithm for cross-referencing biochips.
DAC 2008: 284-289 |
| 187 | EE | Sanjay V. Kumar,
Chandramouli V. Kashyap,
Sachin S. Sapatnekar:
A framework for block-based timing sensitivity analysis.
DAC 2008: 688-693 |
| 186 | EE | Yong Zhan,
Sanjay V. Kumar,
Sachin S. Sapatnekar:
Thermally Aware Design.
Foundations and Trends in Electronic Design Automation 2(3): 255-370 (2008) |
| 185 | EE | Sachin S. Sapatnekar:
Building your yield of dreams.
IEEE Design & Test of Computers 25(2): 194-195 (2008) |
| 184 | EE | Jie Gu,
John Keane,
Sachin S. Sapatnekar,
Chris H. Kim:
Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property.
IEEE Trans. VLSI Syst. 16(2): 206-209 (2008) |
| 183 | EE | Sanjay V. Kumar,
Chris H. Kim,
Sachin S. Sapatnekar:
Body Bias Voltage Computations for Process and Temperature Compensation.
IEEE Trans. VLSI Syst. 16(3): 249-262 (2008) |
| 182 | EE | John Keane,
Hanyong Eom,
Tae-Hyoung Kim,
Sachin S. Sapatnekar,
Chris H. Kim:
Stack Sizing for Optimal Current Drivability in Subthreshold Circuits.
IEEE Trans. VLSI Syst. 16(5): 598-602 (2008) |
| 181 | EE | Jaskirat Singh,
Sachin S. Sapatnekar:
A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and Gaussian Parameter Variations.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 160-173 (2008) |
| 180 | EE | Shrirang K. Karandikar,
Sachin S. Sapatnekar:
Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 45-58 (2008) |
| 179 | EE | Jaskirat Singh,
Zhi-Quan Luo,
Sachin S. Sapatnekar:
A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 295-308 (2008) |
| 178 | EE | Tianpei Zhang,
Sachin S. Sapatnekar:
Buffering global interconnects in structured ASIC design.
Integration 41(2): 171-182 (2008) |
| 177 | EE | Yong Zhan,
Sachin S. Sapatnekar:
Automated module assignment in stacked-Vdd designs for high-efficiency power delivery.
JETC 4(4): (2008) |
| 176 | EE | Haifeng Qian,
Sachin S. Sapatnekar:
Stochastic Preconditioning for Diagonally Dominant Matrices.
SIAM J. Scientific Computing 30(3): 1178-1204 (2008) |
| 2007 |
|---|
| 175 | EE | Felipe S. Marques,
Leomar S. da Rosa Jr.,
Renato P. Ribas,
Sachin S. Sapatnekar,
André Inácio Reis:
DAG based library-free technology mapping.
ACM Great Lakes Symposium on VLSI 2007: 293-298 |
| 174 | EE | Sachin S. Sapatnekar:
Computer-aided design of 3d integrated circuits.
ACM Great Lakes Symposium on VLSI 2007: 317 |
| 173 | EE | Sanjay V. Kumar,
Chris H. Kim,
Sachin S. Sapatnekar:
NBTI-Aware Synthesis of Digital Circuits.
DAC 2007: 370-375 |
| 172 | EE | Qunzeng Liu,
Sachin S. Sapatnekar:
Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations.
DAC 2007: 497-502 |
| 171 | EE | Brent Goplen,
Sachin S. Sapatnekar:
Placement of 3D ICs with Thermal and Interlayer Via Considerations.
DAC 2007: 626-631 |
| 170 | EE | Jie Gu,
Sachin S. Sapatnekar,
Chris H. Kim:
Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift.
DAC 2007: 87-92 |
| 169 | EE | Hushrav Mogal,
Haifeng Qian,
Sachin S. Sapatnekar,
Kia Bazargan:
Clustering based pruning for statistical criticality computation under process variations.
ICCAD 2007: 340-343 |
| 168 | EE | Dmitry Bufistov,
Jordi Cortadella,
Michael Kishinevsky,
Sachin S. Sapatnekar:
A general model for performance optimization of sequential systems.
ICCAD 2007: 362-369 |
| 167 | EE | Yong Zhan,
Tianpei Zhang,
Sachin S. Sapatnekar:
Module assignment for pin-limited designs under the stacked-Vdd paradigm.
ICCAD 2007: 656-659 |
| 166 | EE | Zhuo Li,
Charles J. Alpert,
Stephen T. Quay,
Sachin S. Sapatnekar,
Weiping Shi:
Probabilistic Congestion Prediction with Partial Blockages.
ISQED 2007: 841-846 |
| 165 | EE | Hongliang Chang,
Sachin S. Sapatnekar:
Prediction of leakage power under process uncertainties.
ACM Trans. Design Autom. Electr. Syst. 12(2): (2007) |
| 164 | EE | Sachin S. Sapatnekar:
Book Review: An Assay of Biochips.
IEEE Design & Test of Computers 24(4): 402-403 (2007) |
| 163 | EE | Sachin S. Sapatnekar,
Leon Stok:
DAC Highlights.
IEEE Design & Test of Computers 24(5): 502-504 (2007) |
| 162 | EE | Tianpei Zhang,
Sachin S. Sapatnekar:
Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing.
IEEE Trans. VLSI Syst. 15(6): 624-636 (2007) |
| 161 | EE | Gustavo de Veciana,
Marcello Lajolo,
Chen He,
Enrico Macii,
Sachin S. Sapatnekar:
In Memoriam: Margarida F. Jacome.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1549-1550 (2007) |
| 160 | EE | Yong Zhan,
Sachin S. Sapatnekar:
High-Efficiency Green Function-Based Thermal Simulation Algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1661-1675 (2007) |
| 159 | EE | Krishnendu Chakrabarty,
Sachin S. Sapatnekar:
Editorial to special issue DAC 2006.
JETC 3(3): (2007) |
| 2006 |
|---|
| 158 | EE | Yong Zhan,
Brent Goplen,
Sachin S. Sapatnekar:
Electrothermal analysis and optimization techniques for nanoscale integrated circuits.
ASP-DAC 2006: 219-222 |
| 157 | EE | Tianpei Zhang,
Yong Zhan,
Sachin S. Sapatnekar:
Temperature-aware routing in 3D ICs.
ASP-DAC 2006: 309-314 |
| 156 | EE | Sanjay V. Kumar,
Chris H. Kim,
Sachin S. Sapatnekar:
Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems.
ASP-DAC 2006: 559-564 |
| 155 | EE | Yong Zhan,
Yan Feng,
Sachin S. Sapatnekar:
A fixed-die floorplanning algorithm using an analytical approach.
ASP-DAC 2006: 771-776 |
| 154 | EE | Jaskirat Singh,
Sachin S. Sapatnekar:
Statistical timing analysis with correlated non-gaussian parameters using independent component analysis.
DAC 2006: 155-160 |
| 153 | EE | John Keane,
Hanyong Eom,
Tae-Hyoung Kim,
Sachin S. Sapatnekar,
Chris H. Kim:
Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing.
DAC 2006: 425-428 |
| 152 | EE | Sanjay V. Kumar,
Chris H. Kim,
Sachin S. Sapatnekar:
An analytical model for negative bias temperature instability.
ICCAD 2006: 493-496 |
| 151 | EE | Vidyasagar Nookala,
David J. Lilja,
Sachin S. Sapatnekar:
Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis.
ISLPED 2006: 298-303 |
| 150 | EE | Vidyasagar Nookala,
Ying Chen,
David J. Lilja,
Sachin S. Sapatnekar:
Comparing simulation techniques for microarchitecture-aware floorplanning.
ISPASS 2006: 80-88 |
| 149 | EE | Sanjay V. Kumar,
Chris H. Kim,
Sachin S. Sapatnekar:
Impact of NBTI on SRAM Read Stability and Design for Reliability.
ISQED 2006: 210-218 |
| 148 | EE | Keith A. Bowman,
Michael Orshansky,
Sachin S. Sapatnekar:
Tutorial II: Variability and Its Impact on Design.
ISQED 2006: 5 |
| 147 | EE | Leomar S. da Rosa Jr.,
Felipe S. Marques,
Tiago Muller Gil Cardoso,
Renato P. Ribas,
Sachin S. Sapatnekar,
André Inácio Reis:
Fast disjoint transistor networks from BDDs.
SBCCI 2006: 137-142 |
| 146 | EE | Sachin S. Sapatnekar,
Grant Martin:
DAC Highlights.
IEEE Design & Test of Computers 23(3): 182-184 (2006) |
| 145 | EE | Sachin S. Sapatnekar:
Book Reviews: Plumbing the Depths of Leakage.
IEEE Design & Test of Computers 23(4): 318-319 (2006) |
| 144 | EE | Rupesh S. Shelar,
Prashant Saxena,
Sachin S. Sapatnekar:
Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 625-636 (2006) |
| 143 | EE | Jaskirat Singh,
Sachin S. Sapatnekar:
Partition-Based Algorithm for Power Grid Design Using Locality.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 664-677 (2006) |
| 142 | EE | Brent Goplen,
Sachin S. Sapatnekar:
Placement of Thermal Vias in 3-D ICs Using Various Thermal Objectives.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 692-709 (2006) |
| 141 | EE | Charles J. Alpert,
Jiang Hu,
Sachin S. Sapatnekar,
Cliff C. N. Sze:
Accurate estimation of global buffer delay within a floorplan.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1140-1145 (2006) |
| 2005 |
|---|
| 140 | EE | Felipe S. Marques,
Renato P. Ribas,
Sachin S. Sapatnekar,
André Inácio Reis:
A new approach to the use of satisfiability in false path detection.
ACM Great Lakes Symposium on VLSI 2005: 308-311 |
| 139 | EE | Tianpei Zhang,
Sachin S. Sapatnekar:
Buffering global interconnects in structured ASIC design.
ASP-DAC 2005: 23-26 |
| 138 | EE | Yong Zhan,
Sachin S. Sapatnekar:
Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up.
ASP-DAC 2005: 87-92 |
| 137 | EE | Jaskirat Singh,
Vidyasagar Nookala,
Zhi-Quan Luo,
Sachin S. Sapatnekar:
Robust gate sizing by geometric programming.
DAC 2005: 315-320 |
| 136 | EE | Brent Goplen,
Prashant Saxena,
Sachin S. Sapatnekar:
Net weighting to reduce repeater counts during placement.
DAC 2005: 503-508 |
| 135 | EE | Hongliang Chang,
Sachin S. Sapatnekar:
Full-chip analysis of leakage power under process variations, including spatial correlations.
DAC 2005: 523-528 |
| 134 | EE | Vidyasagar Nookala,
Ying Chen,
David J. Lilja,
Sachin S. Sapatnekar:
Microarchitecture-aware floorplanning using a statistical design of experiments approach.
DAC 2005: 579-584 |
| 133 | | Yong Zhan,
Sachin S. Sapatnekar:
A high efficiency full-chip thermal simulation algorithm.
ICCAD 2005: 635-638 |
| 132 | | Haifeng Qian,
Sachin S. Sapatnekar:
A hybrid linear equation solver and its application in quadratic placement.
ICCAD 2005: 905-909 |
| 131 | EE | Felipe Ribeiro Schneider,
Renato P. Ribas,
Sachin S. Sapatnekar,
André Inácio Reis:
Exact lower bound for the number of switches in series to implement a combinational logic cell.
ICCD 2005: 357-362 |
| 130 | EE | Vidyasagar Nookala,
Sachin S. Sapatnekar:
Designing optimized pipelined global interconnects: algorithms and methodology impact.
ISCAS (1) 2005: 608-611 |
| 129 | EE | Shrirang K. Karandikar,
Sachin S. Sapatnekar:
Fast estimation of area-delay trade-offs in circuit sizing.
ISCAS (4) 2005: 3575-3578 |
| 128 | EE | Rupesh S. Shelar,
Prashant Saxena,
Xinning Wang,
Sachin S. Sapatnekar:
An efficient technology mapping algorithm targeting routing congestion under delay constraints.
ISPD 2005: 137-144 |
| 127 | EE | Brent Goplen,
Sachin S. Sapatnekar:
Thermal via placement in 3D ICs.
ISPD 2005: 167-174 |
| 126 | EE | Jaskirat Singh,
Sachin S. Sapatnekar:
A fast algorithm for power grid design.
ISPD 2005: 70-77 |
| 125 | EE | Sachin S. Sapatnekar,
Jaijeet S. Roychowdhury,
Ramesh Harjani:
High-Speed Interconnect Technology: On-Chip and Off-Chip.
VLSI Design 2005: 7- |
| 124 | EE | Sachin S. Sapatnekar:
An EDA compendium.
IEEE Design & Test of Computers 22(1): 74-75 (2005) |
| 123 | EE | Sachin S. Sapatnekar:
Empowering the designer.
IEEE Design & Test of Computers 22(3): 280-281 (2005) |
| 122 | EE | Sachin S. Sapatnekar,
Kevin J. Nowka:
Guest Editors' Introduction: New Dimensions in 3D Integration.
IEEE Design & Test of Computers 22(6): 496-497 (2005) |
| 121 | EE | Cristinel Ababei,
Yan Feng,
Brent Goplen,
Hushrav Mogal,
Tianpei Zhang,
Kia Bazargan,
Sachin S. Sapatnekar:
Placement and Routing in 3D Integrated Circuits.
IEEE Design & Test of Computers 22(6): 520-531 (2005) |
| 120 | EE | Sachin S. Sapatnekar:
Designing "Vary" Good Circuitry.
IEEE Design & Test of Computers 22(6): 596-597 (2005) |
| 119 | EE | Shrirang K. Karandikar,
Sachin S. Sapatnekar:
Fast comparisons of circuit implementations.
IEEE Trans. VLSI Syst. 13(12): 1329-1339 (2005) |
| 118 | EE | Anup Kumar Sultania,
Dennis Sylvester,
Sachin S. Sapatnekar:
Gate oxide leakage and delay tradeoffs for dual-T/sub ox/ circuits.
IEEE Trans. VLSI Syst. 13(12): 1362-1375 (2005) |
| 117 | EE | Rupesh S. Shelar,
Sachin S. Sapatnekar:
BDD decomposition for delay oriented pass transistor logic synthesis.
IEEE Trans. VLSI Syst. 13(8): 957-970 (2005) |
| 116 | EE | Haifeng Qian,
Sani R. Nassif,
Sachin S. Sapatnekar:
Early-stage power grid analysis for uncertain working modes.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 676-682 (2005) |
| 115 | EE | Jaskirat Singh,
Sachin S. Sapatnekar:
Congestion-aware topology optimization of structured power/ground networks.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 683-695 (2005) |
| 114 | EE | Rupesh S. Shelar,
Sachin S. Sapatnekar,
Prashant Saxena,
Xinning Wang:
A predictive distributed congestion metric with application to technology mapping.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 696-710 (2005) |
| 113 | EE | Haifeng Qian,
Sani R. Nassif,
Sachin S. Sapatnekar:
Power grid analysis using random walks.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(8): 1204-1224 (2005) |
| 112 | EE | Hongliang Chang,
Sachin S. Sapatnekar:
Statistical timing analysis under spatial correlations.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(9): 1467-1482 (2005) |
| 2004 |
|---|
| 111 | EE | Haifeng Qian,
Sachin S. Sapatnekar:
Hierarchical random-walk algorithms for power grid analysis.
ASP-DAC 2004: 499-504 |
| 110 | EE | Vidyasagar Nookala,
Sachin S. Sapatnekar:
A method for correcting the functionality of a wire-pipelined circuit.
DAC 2004: 570-575 |
| 109 | EE | Anup Kumar Sultania,
Dennis Sylvester,
Sachin S. Sapatnekar:
Tradeoffs between date oxide leakage and delay for dual Tox circuits.
DAC 2004: 761-766 |
| 108 | EE | Yong Zhan,
Sachin S. Sapatnekar:
Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming.
DATE 2004: 622-629 |
| 107 | EE | Shrirang K. Karandikar,
Sachin S. Sapatnekar:
Fast Comparisons of Circuit Implementations.
DATE 2004: 910-915 |
| 106 | EE | Haifeng Qian,
Joseph N. Kozhaya,
Sani R. Nassif,
Sachin S. Sapatnekar:
A chip-level electrostatic discharge simulation strategy.
ICCAD 2004: 315-318 |
| 105 | EE | Shrirang K. Karandikar,
Sachin S. Sapatnekar:
Logical effort based technology mapping.
ICCAD 2004: 419-422 |
| 104 | EE | Charles J. Alpert,
Jiang Hu,
Sachin S. Sapatnekar,
Cliff C. N. Sze:
Accurate estimation of global buffer delay within a floorplan.
ICCAD 2004: 706-711 |
| 103 | EE | Anup Kumar Sultania,
Dennis Sylvester,
Sachin S. Sapatnekar:
Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits.
ICCD 2004: 228-233 |
| 102 | EE | Tianpei Zhang,
Sachin S. Sapatnekar:
Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing.
ICCD 2004: 93-98 |
| 101 | EE | Jaskirat Singh,
Sachin S. Sapatnekar:
Topology optimization of structured power/ground networks.
ISPD 2004: 116-123 |
| 100 | EE | Haifeng Qian,
Sani R. Nassif,
Sachin S. Sapatnekar:
Early-stage power grid analysis for uncertain working modes.
ISPD 2004: 132-137 |
| 99 | EE | Rupesh S. Shelar,
Sachin S. Sapatnekar,
Prashant Saxena,
Xinning Wang:
A predictive distributed congestion metric and its application to technology mapping.
ISPD 2004: 210-217 |
| 98 | EE | Hongliang Chang,
Haifeng Qian,
Sachin S. Sapatnekar:
The Certainty of Uncertainty: Randomness in Nanometer Design.
PATMOS 2004: 36-47 |
| 97 | EE | Sachin S. Sapatnekar:
High-Performance Power Grids For Nanometer Technologies.
VLSI Design 2004: 839-844 |
| 96 | EE | Vijay Sundararajan,
Sachin S. Sapatnekar,
Keshab K. Parhi:
A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints.
ACM Trans. Design Autom. Electr. Syst. 9(3): 273-289 (2004) |
| 95 | EE | Haihua Su,
Jiang Hu,
Sachin S. Sapatnekar,
Sani R. Nassif:
A methodology for the simultaneous design of supply and signal networks.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1614-1624 (2004) |
| 2003 |
|---|
| 94 | EE | Haifeng Qian,
Sani R. Nassif,
Sachin S. Sapatnekar:
Random walks in a supply network.
DAC 2003: 93-98 |
| 93 | EE | Hongliang Chang,
Sachin S. Sapatnekar:
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal.
ICCAD 2003: 621-626 |
| 92 | EE | Brent Goplen,
Sachin S. Sapatnekar:
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach.
ICCAD 2003: 86-90 |
| 91 | EE | Venkatesan Rajappan,
Sachin S. Sapatnekar:
An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk.
ICCD 2003: 76- |
| 90 | EE | Haitian Hu,
David Blaauw,
Vladimir Zolotov,
Kaushik Gala,
Min Zhao,
Rajendran Panda,
Sachin S. Sapatnekar:
Table look-up based compact modeling for on-chip interconnect timing and noise analysis.
ISCAS (4) 2003: 668-671 |
| 89 | EE | Guoqiang Chen,
Sachin S. Sapatnekar:
Partition-driven standard cell thermal placement.
ISPD 2003: 75-80 |
| 88 | EE | Sachin S. Sapatnekar,
Haihua Su:
Analysis and Optimization of Power Grids.
IEEE Design & Test of Computers 20(3): 7-15 (2003) |
| 87 | EE | Shrirang K. Karandikar,
Sachin S. Sapatnekar:
Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect.
IEEE Trans. VLSI Syst. 11(6): 1094-1105 (2003) |
| 86 | EE | Haitian Hu,
David T. Blaauw,
Vladimir Zolotov,
Kaushik Gala,
Min Zhao,
Rajendran Panda,
Sachin S. Sapatnekar:
Fast on-chip inductance simulation using a precorrected-FFT method.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 49-66 (2003) |
| 85 | EE | Haihua Su,
Kaushik Gala,
Sachin S. Sapatnekar:
Analysis and optimization of structured power/ground networks.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1533-1544 (2003) |
| 84 | EE | Charles J. Alpert,
Sachin S. Sapatnekar:
Guest editorial.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 385-386 (2003) |
| 83 | EE | Haihua Su,
Sachin S. Sapatnekar,
Sani R. Nassif:
Optimal decoupling capacitor sizing and placement for standard-cell layout designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 428-436 (2003) |
| 82 | EE | Charles J. Alpert,
Jiang Hu,
Sachin S. Sapatnekar,
Paul Villarrubia:
A practical methodology for early buffer and wire resource allocation.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 573-583 (2003) |
| 2002 |
|---|
| 81 | EE | Haihua Su,
Jiang Hu,
Sachin S. Sapatnekar,
Sani R. Nassif:
Congestion-driven codesign of power and signal networks.
DAC 2002: 64-69 |
| 80 | EE | Haitian Hu,
David Blaauw,
Vladimir Zolotov,
Kaushik Gala,
Min Zhao,
Rajendran Panda,
Sachin S. Sapatnekar:
A precorrected-FFT method for simulating on-chip inductance.
ICCAD 2002: 221-227 |
| 79 | EE | Mahesh Ketkar,
Sachin S. Sapatnekar:
Standby power optimization via transistor sizing and dual threshold voltage assignment.
ICCAD 2002: 375-378 |
| 78 | EE | Haitian Hu,
Sachin S. Sapatnekar:
Efficient PEEC-Based Inductance Extraction Using Circuit-Aware Techniques.
ICCD 2002: 434- |
| 77 | EE | Haihua Su,
Sachin S. Sapatnekar,
Sani R. Nassif:
An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts.
ISPD 2002: 68-73 |
| 76 | | Rupesh S. Shelar,
Sachin S. Sapatnekar:
Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits.
IWLS 2002: 209-214 |
| 75 | EE | Tianpei Zhang,
Sachin S. Sapatnekar:
Optimized pin assignment for lower routing congestion after floorplanning phase.
SLIP 2002: 17-21 |
| 74 | EE | Rupesh S. Shelar,
Sachin S. Sapatnekar:
An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis.
VLSI Design 2002: 87-92 |
| 73 | EE | Min Zhao,
Sachin S. Sapatnekar:
Technology mapping algorithms for domino logic.
ACM Trans. Design Autom. Electr. Syst. 7(2): 306-335 (2002) |
| 72 | EE | Jatuchai Pangjun,
Sachin S. Sapatnekar:
Low-power clock distribution using multiple voltages and reduced swings.
IEEE Trans. VLSI Syst. 10(3): 309-318 (2002) |
| 71 | EE | Haitian Hu,
Sachin S. Sapatnekar:
Efficient inductance extraction using circuit-aware techniques.
IEEE Trans. VLSI Syst. 10(6): 746-761 (2002) |
| 70 | EE | Min Zhao,
Rajendran Panda,
Sachin S. Sapatnekar,
David T. Blaauw:
Hierarchical analysis of power distribution networks.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 159-168 (2002) |
| 69 | EE | Vijay Sundararajan,
Sachin S. Sapatnekar,
Keshab K. Parhi:
Fast and exact transistor sizing based on iterative relaxation.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(5): 568-581 (2002) |
| 68 | EE | Jiang Hu,
Sachin S. Sapatnekar:
A timing-constrained simultaneous global routing algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1025-1036 (2002) |
| 67 | EE | Suresh Raman,
Sachin S. Sapatnekar,
Charles J. Alpert:
Probability-driven routing in a datapath environment.
Integration 31(2): 159-182 (2002) |
| 2001 |
|---|
| 66 | EE | Charles J. Alpert,
Jiang Hu,
Sachin S. Sapatnekar,
Paul Villarrubia:
A Practical Methodology for Early Buffer and Wire Resource Allocation.
DAC 2001: 189-194 |
| 65 | EE | Min Zhao,
Sachin S. Sapatnekar:
A New Structural Pattern Matching Algorithm for Technology Mapping.
DAC 2001: 371-376 |
| 64 | EE | Shrirang K. Karandikar,
Sachin S. Sapatnekar:
Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect.
DAC 2001: 377-382 |
| 63 | EE | Haihua Su,
Sachin S. Sapatnekar:
Hybrid Structured Clock Network Construction.
ICCAD 2001: 333-336 |
| 62 | EE | Rupesh S. Shelar,
Sachin S. Sapatnekar:
Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits.
ICCAD 2001: 449-452 |
| 61 | | Jiang Hu,
Sachin S. Sapatnekar:
Performance Driven Global Routing Through Gradual Refinement.
ICCD 2001: 481-483 |
| 60 | EE | Charles J. Alpert,
Gopal Gandham,
Jiang Hu,
José Luis Neves,
Stephen T. Quay,
Sachin S. Sapatnekar:
Steiner tree optimization for buffers. Blockages and bays.
ISCAS (5) 2001: 399-402 |
| 59 | EE | Charles J. Alpert,
Milos Hrkic,
Jiang Hu,
Andrew B. Kahng,
John Lillis,
Bao Liu,
Stephen T. Quay,
Sachin S. Sapatnekar,
A. J. Sullivan,
Paul Villarrubia:
Buffered Steiner trees for difficult instances.
ISPD 2001: 4-9 |
| 58 | | Noel Menezes,
Sachin S. Sapatnekar:
Optimization and Analysis Techniques for the Deep Submicron Regime.
VLSI Design 2001: 3-4 |
| 57 | EE | Yanbin Jiang,
Sachin S. Sapatnekar,
Cyrus Bamji:
Technology mapping for high-performance static CMOS and pass transistor logic designs.
IEEE Trans. VLSI Syst. 9(5): 577-589 (2001) |
| 56 | EE | Charles J. Alpert,
Gopal Gandham,
Jiang Hu,
José Luis Neves,
Stephen T. Quay,
Sachin S. Sapatnekar:
Steiner tree optimization for buffers, blockages, and bays.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(4): 556-562 (2001) |
| 55 | EE | Martin Kuhlmann,
Sachin S. Sapatnekar:
Exact and efficient crosstalk estimation.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(7): 858-866 (2001) |
| 54 | EE | Jiang Hu,
Sachin S. Sapatnekar:
A survey on multi-net global routing for integrated circuits.
Integration 31(1): 1-49 (2001) |
| 2000 |
|---|
| 53 | EE | Min Zhao,
Rajendran Panda,
Sachin S. Sapatnekar,
Tim Edwards,
Rajat Chaudhry,
David Blaauw:
Hierarchical analysis of power distribution networks.
DAC 2000: 150-155 |
| 52 | EE | Vijay Sundararajan,
Sachin S. Sapatnekar,
Keshab K. Parhi:
MINFLOTRANSIT: min-cost flow based transistor sizing tool.
DAC 2000: 649-664 |
| 51 | EE | Mahesh Ketkar,
Kishore Kasamsetty,
Sachin S. Sapatnekar:
Convex delay models for transistor sizing.
DAC 2000: 655-660 |
| 50 | | Haihua Su,
Kaushik Gala,
Sachin S. Sapatnekar:
Fast Analysis and Optimization of Power/Ground Networks.
ICCAD 2000: 477-480 |
| 49 | | Jiang Hu,
Sachin S. Sapatnekar:
A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets.
ICCAD 2000: 99-103 |
| 48 | EE | Suresh Raman,
Sachin S. Sapatnekar,
Charles J. Alpert:
Datapath routing based on a decongestion metric.
ISPD 2000: 122-127 |
| 47 | EE | Sachin S. Sapatnekar:
Capturing the Effect of Crosstalk on Delay.
VLSI Design 2000: 364-369 |
| 46 | EE | Sachin S. Sapatnekar,
Weitong Chuang:
Power-delay optimizations in gate sizing.
ACM Trans. Design Autom. Electr. Syst. 5(1): 98-114 (2000) |
| 45 | EE | Min Zhao,
Sachin S. Sapatnekar:
Timing-driven partitioning and timing optimization of mixedstatic-domino implementations.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1322-1336 (2000) |
| 44 | EE | Jiang Hu,
Sachin S. Sapatnekar:
Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(4): 446-458 (2000) |
| 43 | EE | Sachin S. Sapatnekar:
A timing model incorporating the effect of crosstalk on delay andits application to optimal channel routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 550-559 (2000) |
| 42 | EE | Kishore Kasamsetty,
Mahesh Ketkar,
Sachin S. Sapatnekar:
A new class of convex functions for delay modeling and itsapplication to the transistor sizing problem [CMOS gates].
IEEE Trans. on CAD of Integrated Circuits and Systems 19(7): 779-788 (2000) |
| 1999 |
|---|
| 41 | EE | Jiang Hu,
Sachin S. Sapatnekar:
FAR-DS: Full-Plane AWE Routing with Driver Sizing.
DAC 1999: 84-89 |
| 40 | EE | Yanbin Jiang,
Sachin S. Sapatnekar:
An integrated algorithm for combined placement and libraryless technology mapping.
ICCAD 1999: 102-106 |
| 39 | EE | Min Zhao,
Sachin S. Sapatnekar:
Timing-driven partitioning for two-phase domino and mixed static/domino implementations.
ICCAD 1999: 107-110 |
| 38 | EE | Vijay Sundararajan,
Sachin S. Sapatnekar,
Keshab K. Parhi:
Marsh: min-area retiming with setup and hold constraints.
ICCAD 1999: 2-6 |
| 37 | EE | Martin Kuhlmann,
Sachin S. Sapatnekar,
Keshab K. Parhi:
Efficient Crosstalk Estimation.
ICCD 1999: 266- |
| 36 | EE | Jatuchai Pangjun,
Sachin S. Sapatnekar:
Clock distribution using multiple voltages.
ISLPED 1999: 145-150 |
| 35 | EE | Jiang Hu,
Sachin S. Sapatnekar:
Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model.
ISPD 1999: 133-138 |
| 34 | EE | Huibo Hou,
Jiang Hu,
Sachin S. Sapatnekar:
Non-Hanan routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 436-444 (1999) |
| 33 | EE | Naresh Maheshwari,
Sachin S. Sapatnekar:
Optimizing large multiphase level-clocked circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(9): 1249-1264 (1999) |
| 32 | EE | Naresh Maheshwari,
Sachin S. Sapatnekar:
Retiming control logic.
Integration 28(1): 33-53 (1999) |
| 1998 |
|---|
| 31 | EE | Naresh Maheshwari,
Sachin S. Sapatnekar:
Efficient Minarea Retiming of Large Level-Clocked Circuits.
DATE 1998: 840- |
| 30 | EE | Min Zhao,
Sachin S. Sapatnekar:
Technology mapping for domino logic.
ICCAD 1998: 248-251 |
| 29 | EE | Huibo Hou,
Sachin S. Sapatnekar:
Routing tree topology construction to meet interconnect timing constraints.
ISPD 1998: 205-210 |
| 28 | EE | Naresh Maheshwari,
Sachin S. Sapatnekar:
Efficient retiming of large circuits.
IEEE Trans. VLSI Syst. 6(1): 74-83 (1998) |
| 27 | EE | Yanbin Jiang,
Sachin S. Sapatnekar,
Cyrus Bamji,
Juho Kim:
Interleaving buffer insertion and transistor sizing into a single optimization.
IEEE Trans. VLSI Syst. 6(4): 625-633 (1998) |
| 26 | EE | Harsha Sathyamurthy,
Sachin S. Sapatnekar,
John P. Fishburn:
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(2): 173-182 (1998) |
| 1997 |
|---|
| 25 | EE | Naresh Maheshwari,
Sachin S. Sapatnekar:
An Improved Algorithm for Minimum-Area Retiming.
DAC 1997: 2-7 |
| 24 | EE | Naresh Maheshwari,
Sachin S. Sapatnekar:
Minimum area retiming with equivalent initial states.
ICCAD 1997: 216-219 |
| 23 | EE | Juho Kim,
Cyrus Bamji,
Yanbin Jiang,
Sachin S. Sapatnekar:
Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs.
ISPD 1997: 130-135 |
| 22 | EE | Shankar Ramaswamy,
Sachin S. Sapatnekar,
Prithviraj Banerjee:
A Framework for Exploiting Task and Data Parallelism on Distributed Memory Multicomputers.
IEEE Trans. Parallel Distrib. Syst. 8(11): 1098-1116 (1997) |
| 1996 |
|---|
| 21 | EE | Daksh Lehther,
Sachin S. Sapatnekar:
Clock tree synthesis for multi-chip modules.
ICCAD 1996: 50-53 |
| 20 | EE | Naresh Maheshwari,
Sachin S. Sapatnekar:
A Practical Algorithm for Retiming Level-Clocked Circuits.
ICCD 1996: 440- |
| 19 | EE | Jatan C. Shah,
Sachin S. Sapatnekar:
Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs.
VLSI Design 1996: 346-351 |
| 18 | EE | Sachin S. Sapatnekar,
Rahul B. Deokar:
Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1237-1248 (1996) |
| 17 | EE | Sachin S. Sapatnekar:
Wire sizing as a convex optimization problem: exploring the area-delay tradeoff.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(8): 1001-1011 (1996) |
| 16 | EE | Piyush K. Sancheti,
Sachin S. Sapatnekar:
Optimal design of macrocells for low power and high speed.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1160-1166 (1996) |
| 1995 |
|---|
| 15 | EE | Rahul B. Deokar,
Sachin S. Sapatnekar:
A Fresh Look at Retiming Via Clock Skew Optimization.
DAC 1995: 310-315 |
| 14 | EE | Sachin S. Sapatnekar,
Weitong Chuang:
Power vs. delay in gate sizing: conflicting objectives?
ICCAD 1995: 463-466 |
| 13 | EE | Harsha Sathyamurthy,
Sachin S. Sapatnekar,
John P. Fishburn:
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization.
ICCAD 1995: 467-470 |
| 12 | | Piyush K. Sancheti,
Sachin S. Sapatnekar:
Layout Optimization Using Arbitrarily High Degree Posynomial Models.
ISCAS 1995: 53-56 |
| 11 | EE | Weitong Chuang,
Sachin S. Sapatnekar,
Ibrahim N. Hajj:
Timing and area optimization for standard-cell VLSI circuit design.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 308-320 (1995) |
| 1994 |
|---|
| 10 | EE | Sachin S. Sapatnekar:
RC Interconnect Optimization Under the Elmore Delay Model.
DAC 1994: 387-391 |
| 9 | | Shankar Ramaswamy,
Sachin S. Sapatnekar,
Prithviraj Banerjee:
A Convex Programming Approach for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers.
ICPP 1994: 116-125 |
| 8 | | Jaewon Kim,
Sung-Mo Kang,
Sachin S. Sapatnekar:
High Performance CMOS Macromodule Layout Synthesis.
ISCAS 1994: 179-182 |
| 7 | | Rahul B. Deokar,
Sachin S. Sapatnekar:
A Graph-Theoretic Approach to Clock Skew Optimization.
ISCAS 1994: 407-410 |
| 6 | EE | Sachin S. Sapatnekar,
Pravin M. Vaidya,
Sung-Mo Kang:
Convexity-based algorithms for design centering.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(12): 1536-1549 (1994) |
| 1993 |
|---|
| 5 | EE | Sachin S. Sapatnekar,
Pravin M. Vaidya,
Steve M. Kang:
Convexity-based algorithms for design centering.
ICCAD 1993: 206-209 |
| 4 | EE | Weitong Chuang,
Sachin S. Sapatnekar,
Ibrahim N. Hajj:
A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area.
ICCAD 1993: 220-223 |
| 3 | | Sachin S. Sapatnekar,
Pravin M. Vaidya,
Sung-Mo Kang:
Feasible Region Approximation Using Convex Polytopes.
ISCAS 1993: 1786-1789 |
| 2 | EE | Sachin S. Sapatnekar,
Vasant B. Rao,
Pravin M. Vaidya,
Sung-Mo Kang:
An exact solution to the transistor sizing problem for CMOS circuits using convex optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(11): 1621-1634 (1993) |
| 1991 |
|---|
| 1 | | Sachin S. Sapatnekar,
Vasant B. Rao,
Pravin M. Vaidya:
A Convex Optimization Approach to Transistor Sizing for CMOS Circuits.
ICCAD 1991: 482-485 |
